Standard Products
ACT5271SC Multichip Module Microprocessor
with 2MB Secondary Cache
www.aeroflex.com/Avionics
May 5, 2005
FEATURES
❑
Footprint Compatible with Aeroflex-Plainview original ACT4431SC 1MB Secondary Cache MCM in a
280 lead Ceramic Quad Flat Pack (CQFP)
❑
QED RM5271 Dual Issue superscalar microprocessor - can issue one integer and one floating-point
instruction per cycle
- Max system clock – 25MHz, Max Secondary Cache (SC) clock 75MHz, Max pipeline 150MHz
❑
High performance system interface compatible with R4400
- Internal PLL generates selectable 2x/3x SC bus speed operation vs external system bus speed
- Generates R4400 style system clocks
- CPU cycle rate buffering FIFO implemented in FPGA
- 64-bit multiplexed system address/data bus for optimum price/performance
- High performance write protocols maximize uncached write bandwidth
- Operates at processor clock multipliers 2, 2.5 & 3
❑
Integrated on-chip Primary Caches
- 32KB instruction - 2 way set associative
- 32KB data - 2 way set associative
- Virtually indexed, physically tagged
- Write-back and write-through on per page basis
- Pipeline restart on first double for data cache misses
❑
Integrated in-module Secondary Cache
- 2MB shared write-through
- 4-128K x 36 Synchronous SRAM and 1-64K x 18 Tag RAM
❑
Integrated memory management unit
- Fully associative joint TLB (shared by I and D translations)
- 48 dual entries map 96 pages
- Variable page size (4KB to 16MB in 4x increments)
❑
High-performance floating point unit
- Single cycle repeat rate for common single precision operations and some double precision operations
- Two cycle repeat rate for double precision multiply and double precision combined multiply-add
operations
- Single cycle repeat rate for single precision combined multiply-add operation
❑
MIPS IV instruction set
- Floating point multiply-add instruction increases performance in signal processing and graphics
applications
- Conditional moves to reduce branch frequency
- Index address modes (register + register)
❑
Embedded application enhancements
- Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
- I and D cache locking by set
- Optional dedicated exception vector for interrupts
SCD5271SC Rev B
DESCRIPTION
The ACT-5271SC MCM consists of a QED RM5271 MIPS
microprocessor with 2 MByte of shared, write-through
Secondary Cache. The MCM translates the R4400 style
clocking, bus and modebit information to what the RM5271
expects. This is accomplished by means of a PLL clock
generator, a control CPLD and an FPGA based cycle FIFO.
PINOUT COMPATIBILITY
The ACT-5271SC was designed as a high performance
upgrade replacement for the ACT-4431SC. The 280 lead
flatpack package outline was retained and the pinout is
compatible, with the following exceptions:
■
sequence is followed via ModeClock, ModeIn, ColdResetB
up to when ResetB is deasserted The RM5271 will, in turn,
start its initialization when the internal PLL is Locked and
ColdResetB is deasserted. The CPUs resetb is released with
ResetB after checking to see that the FPGAs have
configured. The actual mode bit stream sent to the RM5271
is created by the internal CPLD with a few pertinent bits
stripped off the incoming stream: Endianness and Secondary
Cache enable. For this design, the interface XmitDatPat is
fixed at DDDD.
CYCLE FIFO
The FIFO, implemented in an FPGA, accepts RM5271 CPU
read and write cycle information direct from the CPU SysAD
bus at the CPU clock rate and retransmits it to the MCM
SysAD at the board’s clock rate. Since the RM5271 does not
normally output parity information on the address phase or
the command bus, the parity information is added to the data
captured from the CPU before it is entered into the FIFO. For
Read data, if bad data is indicated by the Command bus
(bit 5), the parity output to the RM5271 is inverted for that
item, and all remaining ones in the case of a burst. Read
cycles that hit in the Secondary Cache are not entered into
the FIFO.
■
■
■
■
The reassignment of twenty-six - 3.3 volt supply pins
to a core voltage of 2.5 volts.
VccP, the quiet PLL supply is now 2.5 volts
Ten previously unused pins are now used for test
modes and programmable device configuration. They
are pins 171-175, 177, 183, 184, 195 and 196. They
should remain no connects (NC) at the board level.
Certain special R4400 and ACT-4431SC function
signals are not available and are no connects (NC)
within the module substrate. These signals include
IO_IN, IO_OUT, Status[7:0], IVDErrb, IVDAckb,
256K/1MB and FaultB.
The JTAG port does not support complete boundary
scan for the module. The JTAG is used to initialize the
CPLD, which is one component in a chain of four.
CLOCKING AND SPEEDS
The design is tailored towards replacing an ACT-4431SC
device running with a 50 MHz MasterClock (100 MHz
Pipeline Clock) and a TClock /RClock divisor of 4 (25
MHz). In order to mitigate the speed limitation of a 25 MHz
SysAD bus, the ACT-5271SC utilizes a PLL clock multiplier
and CPU cycle FIFO to run the RM5271 and the Secondary
Cache connected to its SysAD bus at a higher rate. For a 25
MHz external bus, the cache bus can run at 50 MHz or 75
MHz (2x or 3x). The RM5271 pipeline can be 2, 2.5 or 3
times the cache speed.
Specifically, the R4400 style MasterClock is buffered and
output as MasterOut. ModeClock is a divide by 256 of
MasterOut. MasterClock is also divided by 2 to produce
RClock, TClock and SyncOut. TClock and SyncOut are
delayed from RClock by one buffer. SyncIn feeds the internal
PLL multiplier circuit which drives the RM5271’s SysClock
and Secondary Cache RAMs at 2x or 3x. The RM5271’s
pipeline frequency is then determined by the modebit
settings generated by the internal CPLD. The two Secondary
Cache multiplier variations are selectable at module pin 195,
for experimentation purposes.
For additional Detail Information regarding the operation of
the Quantum Effect Devices (QED) RISCMark™
RM5271SC™, 64-Bit Superscalar Microprocessor see the
latest QED datasheet (Revision 1.3 2/2000).
START UP SEQUENCE
The process begins with the SRAM based FPGAs loading
from an on-module serial EEPROM when VDDOK is
asserted. At the same time, the standard R4400 startup
SCD5271SC Rev B
3
ABSOLUTE MAXIMUM RATING
1
SYMBOL
PARAMETER
Terminal Voltage with respect to V
SS
Input Voltage Range
Case Operating Temperature under Bias
Storage Temperature
Maximum Power Dissipation
Thermal Resistance (Junction to Case)
Maximum Lead Temperature (10 seconds)
LIMITS
UNITS
V
TERM
V
IN
T
BIAS
T
STG
P
D
Ø
JC
T
L
-0.5
2
to +3.9
-0.5
2
to Vcc+0.5
-55 to +125
-65 to +150
10
2.5
300
V
V
°C
°C
W
°C/W
°C
Note 1: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Note 2: V
IN
minimum = -2.0V for pulse width less than 15ns. V
IN
should not exceed 3.9 Volts.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Supply Ground
Supply Voltage
Supply Voltage for RM5271 Core
Quiet V
CC
for PLL
High Level Input Voltage
Low Level Input Voltage
Case Operating Temperature
MIN
MAX
UNITS
V
SS
V
CC
V
CC
Int
V
CC
P
V
IH
V
IL
T
C
0
3.1
2.4
2.4
2.0
-0.5
-55
3.5
2.6
2.6
Vcc + 0.5
+0.66
+125
V
V
V
V
V
V
°C
Note: 1. V
CC
I/O should not exceed VccInt by greater than 1.2V during the power-up sequence.
2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held low during reset to avoid entering JTAG test mode.
Refer to the RM5200 Family Users Manual, Appendix F.
SCD5271SC Rev B
5
PCB Design
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