IC41C8513 and IC41LV8513
512K x 8 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 1,024 cycles/16 ms
• Refresh Mode:
RAS-Only,
CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
two
CAS
DESCRIPTION
The
ICSI
8513 Series is a 524,288 x 8-bit high-performance
CMOS Dynamic Random Access Memory. The Fast Page
Mode allows 1,024 random accesses within a single row with
access cycle time as short as 12 ns per 8-bit word.
These features make the 8513 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 8513 Series is packaged in a 28-pin 400mil SOJ and a 28
pin TSOP-2
PRODUCT SERIES OVERVIEW
Part No.
IC41C8513
IC41LV8513
Refresh
1K
1K
Voltage
5V ± 10%
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
Fast Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-50
50
14
25
20
90
-60
Unit
60
15
30
25
110
ns
ns
ns
ns
ns
PIN CONFIGURATION
28 Pin SOJ, TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
Functional Description
The IC41C8513 and IC41LV8513 are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 10 address bits. These
are entered 10 bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS
is used to latch the first ten bits and
CAS
is used the
latter nine bits.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period . There are two ways to refresh the memory:
1. By clocking each of the 1,024 row addresses (A0
through A9) with
RAS
at least once every 16 ms . Any
read, write, read-modify-write or
RAS-only
cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs
last.
4
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
IC41C8513 and IC41LV8513
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
−1.0
to +7.0
−0.5
to +4.6
−1.0
to +7.0
−0.5
to +4.6
50
1
0 to +70
−55
to +125
Unit
V
V
mA
W
o
C
o
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
−1.0
−0.3
0
Typ.
5.0
3.3
−
−
−
−
−
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
Unit
V
V
V
o
C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A9
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
o
C, f = 1 MHz.
Integrated Circuit Solution Inc.
DR028-0A 09/25/2001
5
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