Preliminary Information
A
PPLICATION
N
OTE
A V A I L A B L E
AN95 • AN103 • AN107
16K/64K/128K
X84160/640/128
MPS
EEPROM
Advanced MPS™ Micro Port Saver EEPROM with Block Lock™ Protection
FEATURES
• Up to 15MHz data transfer rate
• 20ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—1.8V–3.6V, 2.5V–5.5V and 5V
±
10% Versions
—Standby Current Less than 1
µ
A
—Active Current Less than 1mA
• Byte or Page Write Capable
—32-Byte Page Write Mode
• New Programmable Block Lock™ Protection
—Software Write Protection
—Programmable Hardware Write Protection
• Block Lock (0, 1/4, 1/2, or all of the array)
• Typical Nonvolatile Write Cycle Time: 3ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead Mini-DIP Package
—8, 14-Lead SOIC Packages
—8, 20, 28-Lead TSSOP Packages
—8-Lead XBGA Packages
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 20ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to
15MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line of
the data bus using a sequence of standard bus read and
write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
The X84160/640/128 provide additional data security
features through Block Lock and programmable Hard-
ware Write Protection. These allow some or all of the
array to be write protected by software command or by
hardware. System Configuration, Company ID, calibra-
tion information, or other critical data can be secured
against unexpected or inadvertent program operations,
leaving the remainder of the memory available for the
system or user access
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
Internal Block Diagram MPS
WP
H.V. GENERATION
TIMING & CONTROL
DESCRIPTION
BLOCK DIAGRAM
bs
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
System Connection
µP
µC
A15
O
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
ol
A0
D7
D0
OE
WE
et
e
P
CE
I/O
OE
WE
1
ro
COMMAND
DECODE
AND
CONTROL
LOGIC
Ports
Saved
Xicor, Inc. 1998 Patents Pending
7067 1.1 6/10/98 T10/C0/D3
du
c
X
DEC
Y DECODE
DATA REGISTER
Characteristics subject to change without notice
t
EEPROM
ARRAY
16K x 8
8K x 8
2K x 8
X84160/640/128
PIN CONFIGURATIONS:
Drawings are to the same scale, actual package sizes are shown in inches:
8-LEAD PDIP
8-LEAD SOIC
CE
I/O
WP
V SS
1
2
X84160
3
X84640
4
.230 in.
8
7
6
5
V CC
NC
OE
WE
.190 in.
NC
V
CC
CE
I/O
8-LEAD TSSOP
1
2
3
4
8
7
6
5
OE
WE
WP
VSS
PIN NAMES
.114 in.
X84160
I/O
CE
OE
WE
WP
Data Input/Output
Chip Enable Input
Write Enable Input
Supply Voltage
Ground
No Connect
Output Enable Input
Write Protect Input
14-LEAD SOIC
CE
I/O
NC
NC
NC
WP
V SS
1
2
3
4
5
6
7
.230 in.
X84128
14
13
12
11
10
9
8
V CC
NC
NC
NC
NC
OE
WE
.390 in.
NC
NC
CE
I/O
NC
NC
NC
WP
VSS
NC
1
2
3
4
5
6
7
8
9
10
X84640
20
19
18
17
16
15
14
13
12
11
NC
NC
VCC
NC
NC
NC
NC
OE
WE
NC
.250 in.
ro
NC
NC
NC
NC
V
CC
NC
NC .394 in.
NC
NC
OE
WE
NC
NC
NC
.252 in.
28-LEAD TSSOP
NC
NC
CE
CE
CE
I/O
NC
NC
NC
WP
V
SS
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
8-LEAD XBGA: Top View
VCC 1 8 I/O
.238 in.
NC
WE
OE
2 7 CE
3 6 VSS
4 5 WP
P
2
X84128
e
. 252 in.
.078 in.
PIN DESCRIPTIONS
et
Output Enable (OE)
The Output Enable input must be LOW to enable the out-
put buffer and to read data from the device on the I/O line.
bs
ol
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Write Protect (WP)
The Write Protect input controls the Hardware Write Pro-
tect feature. When WP is LOW and the nonvoltaile bit
WPEN is “1”, nonvolatile writes of the X84160/640/128
control register is disabled, but the part otherwise func-
tions normally. When WP is held HIGH, all functions,
including nonvolatile write operate normally. WP going
LOW while CS is still LOW will interrupt a write to the
X84160/640/128 control register. If the internal Write
cycle has already been initiated, WP going LOW will
have no effect on write.
The WP pin function is blocked when the WPEN bit in the
control register is “0”. This allows the user to install the
X84160/640/128 in a system with WP pin grounded and
still be able to write to the control register. The WP pin
functions will be enabled when the WPEN bit is set “1”.
O
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
du
c
V
CC
V
SS
NC
20-LEAD TSSOP
PACKAGE
SELECTION GUIDE
84160
8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP
8-Lead CSP/BGA
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
8-Lead CSP/BGA
8-Lead PDIP
14-Lead SOIC
28-Lead TSSOP
84640
84128
t
.252 in.
X84160/640/128
DEVICE OPERATION
The X84160/640/128 are serial EEPROMs designed to
interface directly with most microprocessor buses. Stan-
dard CE, OE, and WE signals control the read and write
operations, and a single l/O line is used to send and
receive data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge of
either WE or CE, whichever occurs first. Data output on
the l/O line is active whenever both OE and CE are LOW.
Care should be taken to ensure that WE and OE are
never both LOW while CE is LOW.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle between
the write cycles. The address is sent serially, most signifi-
cant bit first, over the I/O line. Note that this sequence is
fully static, with no special timing restrictions, and the pro-
cessor is free to perform other tasks on the bus when-
ever the device CE pin is HIGH. Once the 16 address
bits are sent, a byte of data can be read on the I/O line by
issuing 8 separate read cycles (OE and CE LOW, WE
HIGH). At this point, writing a ‘1’ will terminate the read
sequence and enter the low power standby state, other-
wise the device will await further reads in the sequential
read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address in the array is reached, the
address counter rolls over to address 0000h and reading
may be continued indefinitely.
Reset Sequence
The reset sequence resets the device and sets an inter-
nal write enable latch. A reset sequence can be sent at
any time by performing a read/write “0”/read operation
(see Figs. 1 and 2). This breaks the multiple read or write
cycle sequences that are normally used to read from or
write to the part. The reset sequence can be used at any
time to interrupt or end a sequential read or page load.
As soon as the write “0” cycle is complete, the part is
reset (unless a nonvolatile write cycle is in progress). The
second read cycle in this sequence, and any further read
cycles, will read a HIGH on the l/O pin until a valid read
sequence (which includes the address) is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the device initiates
these operations properly.
Figure 1. Read Sequence
CE
O
bs
OE
WE
ol
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
et
e
P
3
A7 A6 A5 A4 A3 A2
I/O (OUT)
RESET
WHEN ACCESSING: X84160 ARRAY: A15–A11=0
X84640 ARRAY: A15–A13=0
X84128 ARRAY: A15–A14=0
LOAD ADDRESS
ro
A1 A0
du
c
D7 D6 D5 D4 D3 D2 D1 D0
READ DATA
t
7008 FRM F04.1
X84160/640/128
Figure 2: Write Sequence
CE
OE
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
du
c
D7 D6 D5 D4 D3 D2 D1 D0
RESET
WHEN ACCESSING:
X84160 ARRAY: A15–A11=0
X84640 ARRAY: A15–A13=0
X84128 ARRAY: A15–A14=0
LOAD ADDRESS
ro
I/O (OUT)
LOAD DATA
P
4
et
Write Sequence
A nonvolatile write sequence consists of sending a reset
sequence, a 16-bit address, up to 32 bytes of data, and
then a special “start nonvolatile write cycle” command
sequence.
e
page, where data loading can continue. For this reason,
sending more than 256 consecutive data bits will result in
overwriting previous data.
A nonvolatile write cycle will not start if a partial or incom-
plete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is com-
pleted and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static, with no spe-
cial timing restrictions. The processor is free to perform
other tasks on the bus whenever the chip enable pin (CE)
is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.
The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 32-
byte pages (e.g., beginning at addresses XXXXXX00000
for X84160).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
O
bs
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write enable
latch. The address is written serially by issuing 16
separate write cycles (WE and CE LOW, OE HIGH) to
the part without any read cycles between the writes. The
address is sent serially, most significant bit first, on the
l/O pin. Up to 32 bytes of data are written by issuing a
multiple of 8 write cycles. Again, no read cycles are
allowed between writes.
ol
t
"1"
"0"
START
NONVOLATILE
WRITE
7008 FRM F05.1
X84160/640/128
CONTROL REGISTER
The X84160/640/128 has one register that contains
control bits for the devices. The control bits, WPEN, BP1,
and BP0, are shown in Table 1. To read or change the
contents of this register requires a one byte operation to
address FFFFh.
A read from FFFFh returns the one byte contents of the
control register unused bits return 0. Continued reads
return undefined data. A write to address FFFFh changes
the value of the bits. Unused bits are written as “0”.
Writing more than one byte to the control register is a
violation and the operation will be aborted. After sending
one byte to the control register, a start nonvolatile write
cycle will latch in the new state.
Table 1
7
WPEN
6
0
5
0
4
0
3
BP1
2
BP0
1
0
0
0
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register control
the programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware write protection
is disabled when either the WP pin is HIGH or the WPEN
bit is “0”. When the chip is hardware write protected,
nonvolatile write is disabled to the Control Register,
including the Block Protect bits and the WPEN bit itself,
as well as the block-protected sections in the memory
array. Only the sections of the memory array that are not
block-protected can be written.
Note:
When the WP pin is tied to V
SS
and the WPEN bit is HIGH, the
WPEN bit is write protected. It cannot be changed back to a
“0”, as long as the WP pin is held LOW.
WPEN
0
1
X
WP
X
LOW
HIGH
Protected
Blocks
Protected
Protected
Protected
Unprotected
Blocks
Writable
Writable
Table 3. Block Lock Protection
bs
Control Register Bits
BP1
0
0
BP0
0
1
ol
et
Writable
e
WPEN: Write Protect Enable Bit
The Write-Protect-Enable (WPEN) bit is an enable bit for
the WP pin.
Table 2
Status
Register
Writable
The Block Protect (BP0 and BP1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X84160/640/128 is divided into four segments. One,
two, or all four of the segments may be protected. That is,
the user may read the segments but will be unable to
alter (write) data within the selected segments. The
partitioning is controlled as illustrated in table 3 below.
Protected
Writable
X84160
None
0600h–07FFh
0400h–07FFh
0000–07FFh
P
X84640
None
5
Array Address Protected
X84128
None
3000h–3FFFh
2000h–3FFFh
0000h–3FFFh
upper 1/4
upper 1/2
Full Array
(Not including the
control register.)
Array
1800h–1FFFh
1000h–1FFFh
0000–1FFFh
O
1
1
0
1
ro
BP1, BP0: Block Protect Bits
du
c
t
京公网安备 11010802033920号
EEWORLD
