and IOVDD to GND ..................................................... –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +V
CC
+ 0.3V
Digital Inputs to GND .......................................... –0.3V to IOVDD + 0.3V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ....................................... –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above these ratings can cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
(1)
NOMINAL
PENIRQ
PULLUP
RESISTOR
VALUES
50kΩ
90kΩ
50kΩ
MAXIMUM
INTEGRAL
LINEARITY
PACKAGE
ERROR (LSB) PACKAGE-LEAD DESIGNATOR
±2
±2
±2
VFBGA-48
VFBGA-48
TSSOP-16
GQC
GQC
PW
PRODUCT
TSC2046
TSC2046-90
TSC2046
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
PACKAGE
MARKING
AZ2046
AZ2046A
TSC2046I
ORDERING
NUMBER
TSC2046IGQCR
TSC2046IGQCR-90
TSC2046IPW
TSC2046IPWR
TSC2046IRGVT
TSC2046IRGVR
TRANSPORT
MEDIA, QUANTITY
Tape and Reel, 2500
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
"
TSC2046
"
50kΩ
"
±2
"
QFN-16
"
RGV
"
–40°C to +85°C
"
TSC2046
"
"
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet.
2
TSC2046
www.ti.com
SBAS265C
ELECTRICAL CHARACTERISTICS
At T
A
= –40°C to +85°C, +V
CC
= +2.7V, V
REF
= 2.5V internal voltage, f
SAMPLE
= 125kHz, f
CLK
= 16 • f
SAMPLE
= 2MHz, 12-bit mode, digital inputs = GND or IOVDD,
and +V
CC
must be • IOVDD, unless otherwise noted.
TSC2046
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Capacitance
Leakage Current
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Offset Error
Gain Error
Noise
Power-Supply Rejection
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
SWITCH DRIVERS
On-Resistance
Y+, X+
Y–, X–
Drive Current
(2)
REFERENCE OUTPUT
Internal Reference Voltage
Internal Reference Drift
Quiescent Current
REFERENCE INPUT
Range
Input Impedance
CONDITIONS
Positive Input-Negative Input
Positive Input
Negative Input
MIN
0
–0.2
–0.2
25
0.1
12
11
±2
±6
±4
70
70
12
3
125
500
30
100
100
TYP
MAX
V
REF
+V
CC
+ 0.2
+0.2
UNITS
V
V
V
pF
µA
Bits
Bits
LSB
(1)
LSB
LSB
µVrms
dB
CLK Cycles
CLK Cycles
kHz
ns
ns
ps
dB
External V
REF
Including Internal V
REF
V
IN
= 2.5Vp-p at 50kHz
5
6
Duration 100ms
2.45
2.50
15
500
50
2.55
Ω
Ω
mA
V
ppm/°C
µA
V
GΩ
Ω
1.0
SER/DFR = 0, PD1 = 0,
Internal Reference Off
Internal Reference On
0.5
10
1
V
BAT
= 0.5V to 5.5V, External V
REF
= 2.5V
V
BAT
= 0.5V to 5.5V, Internal Reference
–2
–3
–40°C
Differential Method
(3)
TEMP0
(4)
Differential Method
(3)
TEMP0
(4)
1.6
0.3
±2
±3
CMOS
| I
IH
|
≤
+5µA
| I
IL
|
≤
+5µA
I
OH
= –250µA
I
OL
= 250µA
IOVDD • 0.7
–0.3
IOVDD • 0.8
Straight Binary
Specified Performance
Operating Range
Internal Reference Off
Internal Reference On
f
SAMPLE
= 12.5kHz
Power-Down Mode with
CS = DCLK = DIN = IOVDD
+V
CC
= +2.7V
–40
2.7
2.2
1.5
280
780
220
1
250
+V
CC
BATTERY MONITOR
Input Voltage Range
Input Impedance
Sampling Battery
Battery Monitor Off
Accuracy
TEMPERATURE MEASUREMENT
Temperature Range
Resolution
Accuracy
DIGITAL INPUT/OUTPUT
Logic Family
V
IH
V
IL
V
OH
V
OL
Data Format
POWER-SUPPLY REQUIREMENTS
+V
CC(5)
IOVDD
(6)
Quiescent Current
(7)
6.0
V
kΩ
GΩ
%
%
°C
°C
°C
°C
°C
+2
+3
+85
IOVDD + 0.3
0.3 • IOVDD
0.4
V
V
V
V
3.6
5.25
+V
CC
650
3
1.8
+85
V
V
V
µA
µA
µA
µA
mW
°C
Power Dissipation
TEMPERATURE RANGE
Specified Performance
NOTES: (1) LSB means least significant bit. With V
REF
= +2.5V, one LSB is 610µV. (2) Assured by design, but not tested. Exceeding 50mA source current may result
in device degradation. (3) Difference between TEMP0 and TEMP1 measurement, no calibration necessary. (4) Temperature drift is –2.1mV/°C. (5) TSC2046 operates
down to 2.2V. (6) IOVDD must be - +V
CC
. (7) Combined supply current from +V
CC
and IOVDD. Typical values obtained from conversions on AUX input with
PD0 = 0.
TSC2046
SBAS265C
www.ti.com
3
PIN CONFIGURATION
Top View
TSSOP
Top View
DCLK
CS
DIN
BUSY DOUT
VFBGA
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
1
2
3
4
5
6
7
8
TSC2046
16
15
14
13
12
11
10
9
DCLK
CS
DIN
BUSY
+V
CC
B
NC
NC
NC
NC
NC
PENIRQ
C
+V
CC
D
NC
NC
NC
NC
NC
V
REF
E
Y+
F NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AUX
X+
NC
NC
NC
NC
IOVDD
1
A NC
2
3
4
5
6
7
NC
DOUT
PENIRQ
IOVDD
V
REF
G NC
NC
X–
Y–
GND
GND
V
BAT
Top View
15 PENIRQ
TSSOP
14 IOVDD
16 DOUT
BUSY
DIN
CS
DCLK
1
2
TSC2046
3
4
13 V
REF
12
11
10
9
AUX
V
BAT
GND
Y–
5
6
7
Y+
+V
CC
X+
PIN DESCRIPTION
TSSOP PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VFBGA PIN #
B1 and C1
D1
E1
G2
G3
G4 and G5
G6
E7
D7
C7
B7
A6
A5
A4
A3
A2
QFN PIN #
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
NAME
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
V
REF
IOVDD
PENIRQ
DOUT
BUSY
DIN
CS
DCLK
DESCRIPTION
Power Supply
X+ Position Input
Y+ Position Input
X– Position Input
Y– Position Input
Ground
Battery Monitor Input
Auxiliary Input to ADC
Voltage Reference Input/Output
Digital I/O Power Supply
Pen Interrupt
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
Busy Output. This output is high impedance when CS is high.
Serial Data Input. If CS is low, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
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