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MPC8306S: DescriptionPowerQUICC II Pro Processor; File Size436KB，70 Pages; ManufacturerFREESCALE (NXP)

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MPC8306S Overview

PowerQUICC II Pro Processor

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Freescale Semiconductor

Technical Data

Document Number: MPC8306SEC

Rev. 1, 09/2011

MPC8306S

PowerQUICC II Pro Integrated

Communications Processor

Family Hardware Specifications

This document provides an overview of the

MPC8306S

PowerQUICC II Pro

processor features. The MPC8306S is

a cost-effective, highly integrated communications

processor that addresses the requirements of several

networking applications, including residential gateways,

modem/routers, industrial control, and test and measurement

applications. The MPC8306S extends current PowerQUICC

offerings, adding higher CPU performance, additional

functionality, and faster interfaces, while addressing the

requirements related to time-to-market, price, power

consumption, and board real estate. This document describes

the electrical characteristics of MPC8306S.

To locate published errata or updates for this document, refer

to the MPC8306S product summary page on our website

listed on the back cover of this document or contact your

local Freescale sales office.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12

DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ethernet and MII Management . . . . . . . . . . . . . . . . . 21

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 44

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

System Design Information . . . . . . . . . . . . . . . . . . . 64

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 67

Document Revision History . . . . . . . . . . . . . . . . . . . 69

Overview

In summary, the MPC8306S provides users with a highly integrated, fully programmable communications

processor. This helps to ensure that a low-cost system solution can be quickly developed and offers

flexibility to accommodate new standards and evolving system requirements.

1.1

Features

The major features of the device are as follows:

• e300c3 Power Architecture processor core

— Enhanced version of the MPC603e core

— High-performance, superscalar processor core with a four-stage pipeline and low interrupt

latency times

— Floating-point, dual integer units, load/store, system register, and branch processing units

— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

— Dynamic power management

— Enhanced hardware program debug features

— Software-compatible with Freescale processor families implementing Power Architecture

technology

— Separate PLL that is clocked by the system bus clock

— Performance monitor

• QUICC Engine block

— 32-bit RISC controller for flexible support of the communications peripherals with the

following features:

– One clock per instruction

– Separate PLL for operating frequency that is independent of system’s bus and e300 core

frequency for power and performance optimization

– 32-bit instruction object code

– Executes code from internal IRAM

– 32-bit arithmetic logic unit (ALU) data path

– Modular architecture allowing for easy functional enhancements

– Slave bus for CPU access of registers and multiuser RAM space

– 48 Kbytes of instruction RAM

– 16 Kbytes of multiuser data RAM

– Serial DMA channel for receive and transmit on all serial channels

— Five unified communication controllers (UCCs) supporting the following protocols and

interfaces:

– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.

– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)

– HDLC Bus (bit rate up to 10 Mbps)

– Asynchronous HDLC (bit rate up to 2 Mbps)

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

MPC8306S Related Products

	MPC8306S	MAPBGA	MPC8306SEC
Description	PowerQUICC II Pro Processor	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

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