®
KAD5610P
Data Sheet
September 10, 2009
FN6810.2
Dual 10-Bit, 250/210/170/125MSPS A/D
Converter
The KAD5610P is a family of low-power, high-performance,
dual-channel 10-bit, analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates
of up to 250MSPS. The KAD5610P-25 is the fastest member
of this pin-compatible family, which also features sample
rates of 210MSPS (KAD5610P-21), 170MSPS
(KAD5610P-17) and 125MSPS (KAD5610P-12).
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of gain, skew and offset
matching between the two converter cores.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5610P is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
CLKDIV
OVDD
AVDD
Features
• Programmable Gain, Offset and Skew control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider:
÷1, ÷2
or
÷4
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHs Compliant)
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
CLKP
CLKN
CLOCK
GENERATION
CLKOUTP
CLKOUTN
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
• WiMAX and Microwave Receivers
AINP
SHA
AINN
10-BIT
250MSPS
ADC
VREF
DIGITAL
ERROR
CORRECTION
D[9:0]P
D[9:0]N
ORP
ORN
OUTFMT
OUTMODE
Key Specifications
• SNR = 60.7dBFS for f
IN
= 105MHz (-1dBFS)
• SFDR = 86.1dBc for f
IN
= 105MHz (-1dBFS)
• Power Consumption
- 411mW @ 250MSPS
- 327mW @ 125MSPS
VCM
BINP
SHA
BINN
10-BIT
250MSPS
ADC
VREF
1.25V
+
–
SPI
CONTROL
Pin-Compatible Family
MODEL
RESOLUTION
12
12
12
12
10
10
10
10
SPEED
(MSPS)
250
210
170
125
250
210
170
125
RESETN
CSB
SCLK
SDIO
SDO
NAPSLP
OVSS
AVSS
KAD5612P-25
KAD5612P-21
KAD5612P-17
KAD5612P-12
KAD5610P-25
KAD5610P-21
KAD5610P-17
KAD5610P-12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5610P
Ordering Information
PART NUMBER
(Note 1)
KAD5610P-25Q72
KAD5610P-21Q72
KAD5610P-17Q72
KAD5610P-12Q72
NOTE:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART MARKING
KAD5610P-25 Q72EP-I
KAD5610P-21 Q72EP-I
KAD5610P-17 Q72EP-I
KAD5610P-12 Q72EP-I
SPEED
(MSPS)
250
210
170
125
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-Free)
72 Ld QFN
72 Ld QFN
72 Ld QFN
72 Ld QFN
PKG. DWG. #
L72.10x10D
L72.10x10D
L72.10x10D
L72.10x10D
2
FN6810.2
September 10, 2009
KAD5610P
Table of Contents
Absolute Maximum Ratings ......................................... 4
Thermal Information...................................................... 4
Operating Conditions.................................................... 4
Electrical Specifications4
Digital Specifications .................................................... 6
Timing Diagrams ........................................................... 7
Switching Specifications .............................................. 7
Pinout/Package Information......................................... 8
Pin Descriptions.......................................................... 8
Pinout ......................................................................... 10
Typical Performance Curves ........................................ 11
Theory of Operation ...................................................... 14
Functional Description ................................................
Power-On Calibration .................................................
User-Initiated Reset....................................................
Analog Input ...............................................................
Clock Input .................................................................
Jitter............................................................................
Voltage Reference......................................................
Digital Outputs ............................................................
Over-Range Indicator .................................................
14
14
15
15
16
16
17
17
17
Power Dissipation ...................................................... 17
Nap/Sleep .................................................................. 17
Data Format ............................................................... 18
Serial Peripheral Interface ........................................... 21
SPI Physical Interface................................................
SPI Configuration.......................................................
Device Information .....................................................
Indexed Device Configuration/Control .......................
Global Device Configuration/Control..........................
Device Test ................................................................
SPI Memory Map .......................................................
21
21
22
22
23
24
25
Equivalent Circuits ....................................................... 26
ADC Evaluation Platform ............................................. 27
Layout Considerations................................................. 27
Split Ground and Power Planes.................................
Clock Input Considerations ........................................
Exposed Paddle.........................................................
Bypass and Filtering ..................................................
LVDS Outputs ............................................................
LVCMOS Outputs ......................................................
Unused Inputs............................................................
27
27
27
27
27
28
28
Definitions ..................................................................... 28
Revision History ........................................................... 29
3
FN6810.2
September 10, 2009
KAD5610P
Absolute Maximum Ratings
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Information
Thermal Resistance (Typical), Note 2)
θ
JA
(°C/W)
72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, f
SAMPLE
= Maximum Conversion Rate (per
speed grade).
KAD5610P-25
(Note 3)
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
KAD5610P-21
(Note 3)
MIN
TYP
MAX
KAD5610P-17
(Note 3)
MIN
TYP
MAX
KAD5610P-12
(Note 3)
MIN
TYP
MAX UNITS
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
Input Resistance
Input Capacitance
Full Scale Range
Temp. Drift
Input Offset Voltage
Gain Error
Common-Mode
Output Voltage
Clock Inputs
Inputs Common
Mode Voltage
CLKP,CLKN Input
Swing
Power Requirements
1.8V Analog Supply
Voltage
1.8V Digital Supply
Voltage
1.8V Analog Supply
Current
1.8V Digital Supply
Current (Note 4)
Power Supply
Rejection Ratio
AVDD
OVDD
IAVDD
I
OVDD
V
FS
R
IN
C
IN
A
VTC
V
OS
E
G
V
CM
Differential
Differential
Differential
Full Temp
1.4
1.47
1000
1.8
90
1.54
1.4
1.47
1000
1.8
90
1.54
1.4
1.47
1000
1.8
90
1.54
1.4
1.47
1000
1.8
90
1.54
V
P-P
Ω
pF
ppm/°
C
-10
±2
±2
10
-10
±2
±0.6
10
-10
±2
±0.6
10
-10
±2
±0.6
10
mV
%
435
535
635
435
535
635
435
535
635
435
535
635
mV
0.9
1.8
0.9
1.8
0.9
1.8
0.9
1.8
V
V
1.7
1.7
1.8
1.8
170
1.9
1.9
177
65
1.7
1.7
1.8
1.8
158
57
-36
1.9
1.9
165
63
1.7
1.7
1.8
1.8
142
55
-36
1.9
1.9
152
62
1.7
1.7
1.8
1.8
128
53
-36
1.9
1.9
135
60
V
V
mA
mA
dB
3mA LVDS
30MHz,
200mV
P-P
signal on
AVDD
58
-36
PSRR
4
FN6810.2
September 10, 2009
KAD5610P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, f
SAMPLE
= Maximum Conversion Rate (per
speed grade).
(Continued)
KAD5610P-25
(Note 3)
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
KAD5610P-21
(Note 3)
MIN
TYP
MAX
KAD5610P-17
(Note 3)
MIN
TYP
MAX
KAD5610P-12
(Note 3)
MIN
TYP
MAX UNITS
Total Power Dissipation
Normal Mode
Nap Mode
Sleep Mode
Nap Mode Wakeup
Time (Note 5 )
Sleep Mode
Wakeup Time
(Note 5)
AC SPECIFICATIONS
Differential
Nonlinearity
Integral
Nonlinearity
Minimum
Conversion Rate
(Note 6)
Maximum
Conversion Rate
Signal-to-Noise
Ratio
DNL
INL
f
S
MIN
-0.5
-0.75
±0.1
2
±0.2
0.5
0.75
40
-0.5
-0.75
±0.17
±0.3
0.5
0.75
40
-0.5
-0.75
±0.1
7
±0.3
0.5
-0.5
±0.1
7
±0.3
0.5
0.75
40
LSB
LSB
MSPS
PD
PD
PD
CSB at logic
high
Sample Clock
Running
Sample Clock
Running
3mA LVDS
411
148
2
1
1
438
163
6
387
142
2
1
1
411
157
6
357
136
2
1
1
387
151
6
327
129
2
1
1
351
143
6
mW
mW
mW
µs
ms
0.75 -0.75
40
f
S
MAX
SNR
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
250
60.8
59.5
60.7
60.6
60.5
59.9
59.1
60.7
59.3
60.7
60.5
60.4
56.5
49.8
9.8
9.5
9.8
9.8
9.7
9.1
8.0
83.0
70.0
86.1
78.0
76.2
60.8
50.2
210
60.8
60.0
60.9
60.8
60.6
60.0
59.2
60.8
59.9
60.9
60.8
60.5
57.3
46.9
9.8
9.6
9.8
9.8
9.8
9.2
7.5
82.0
70.0
86.6
80.1
77.1
61.9
47.2
170
61.0
60.2
61.0
60.9
60.7
60.1
59.3
60.9
60.0
60.9
60.8
60.6
56.9
47.7
9.8
9.6
9.8
9.8
9.8
9.2
7.6
78.0
70.0
84.6
81.0
77.9
61.0
47.9
125
61.0
60.2
61.0
60.9
60.7
60.0
59.2
61.0
60.0
61.0
60.9
60.4
56.6
49.1
9.8
9.6
9.8
9.8
9.7
9.1
7.9
79.0
70.0
85.8
81.2
72.1
61.1
49.4
MSPS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
Signal-to-Noise and
Distortion
SINAD
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Effective Number of
Bits
ENOB
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Spurious-Free
Dynamic Range
SFDR
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
5
FN6810.2
September 10, 2009
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