X9258
Low Noise/Low Power/2-Wire Bus/256 Taps
Data Sheet
April 14, 2011
FN8168.5
Quad Digital Controlled Potentiometers
(XDCP™)
The X9258 integrates 4 digitally controlled potentiometers
(XDCP™) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 non-volatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power-up
recalls the contents of DR0 to the WCR.
The XDCP™ can be used as a three-terminal potentiometer
or as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four potentiometers in one package
• 256 resistor taps/potentiometer................. 0.4% resolution
• 2-wire serial interface
• Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of wiper position
• Standby current <5µA max (total package)
• Power supplies
- V
CC
= 2.7V to 5.5V
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• 100kΩ, 50kΩ total potentiometer resistance
• High reliability
- Endurance: 100,000 data changes per bit per register
- Register data retention . . . . . . . . . . . . . . . . . . 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9259
• Pb-free available (RoHS compliant)
Block Diagram
V
CC
V
SS
V+
V-
WP
SCL
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
R
2
R
3
R
0
R
1
WIPER
COUNTER
REGISTER
(WCR)
POT 0
V
H0
/R
H0
R
0
R
1
WIPER
COUNTER
REGISTER
(WCR)
V
H2
/R
H2
RESISTOR
ARRAY
POT 2
V
L0
/R
L0
V
W0
/R
W0
R
2
R
3
V
L2
/R
L2
V
W2
/R
W2
8
DATA
R
0
R
1
WIPER
COUNTER
REGISTER
(WCR)
V
W1
/R
W1
V
H1
/R
H1
R
0
R
1
V
W3
/R
W3
WIPER
COUNTER
REGISTER
(WCR)
V
H3
/R
H3
RESISTOR
ARRAY
POT 1
R
2
R
3
RESISTOR
ARRAY
POT 3
V
L1
/R
L1
R
2
R
3
V
L3
/R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2005, 2006, 2011. All Rights Reserved
XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9258
Ordering Information
PART NUMBER
X9258US24*
,
**
X9258US24Z*
,
** (Note)
X9258US24I*
,
**
X9258US24IZ*
,
** (Note)
X9258UV24
X9258UV24I
X9258UV24IZ (Note)
X9258TS24*
X9258TS24Z (Note)
X9258TS24I*
X9258TS24IZ* (Note)
X9258TV24
X9258TV24I
X9258US24-2.7*
X9258US24Z-2.7* (Note)
X9258US24I-2.7*
PART
MARKING
X9258US
X9258US Z
X9258US I
X9258US ZI
X9258UV
X9258UV I
X9258UV ZI
X9258TS
X9258TS Z
X9258TS I
X9258TS ZI
X9258TV
X9258TV I
X9258US F
X9258US ZF
X9258US G
2.7 to 5.5
100
50
V
CC
LIMITS
(V)
5 ±10
POTENTIOMETER TEMPERATURE
RANGE
ORGANIZATION
(°C)
(kΩ)
100
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
50
0 to +70
-40 to +85
-40 to +85
100
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
0 to +70
PACKAGE
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
PKG.
DWG. #
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
X9258US24IZ-2.7*
,
** (Note) X9258US ZG
X9258UV24-2.7*
X9258UV24I-2.7
X9258UV24IZ-2.7 (Note)
X9258TS24-2.7*
X9258TS24Z-2.7* (Note)
X9258TS24I-2.7*
X9258TS24IZ-2.7* (Note)
X9258TV24-2.7
X9258TV24I-2.7
X9258TV24IZ-2.7 (Note)
X9258TV24Z-2.7 (Note)
X9258UV F
X9258UV G
X9258UV ZG
X9258TS F
X9258TS ZF
X9258TS G
X9258TS ZG
X9258TV F
X9258TV G
X9258TV ZG
X9258TV ZF
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
M24.3
M24.3
M24.3
M24.3
MDP0044
MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
2
FN8168.5
April 14, 2011
X9258
Pinout
X9258
(24 LD SOIC, TSSOP)
TOP VIEW
NC
A0
V
W3
/R
W3
V
H3
/R
H3
V
L3
/R
L3
V+
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
A2
WP
1
2
3
4
5
6
7
8
9
10
11
12
X9258
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
V
L2
/R
L2
V
H2
/R
H2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
A1
SDA
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the
X9258.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to “Guidelines for
Calculating Typical Values of Bus Pull-Up Resistors” on
page 10.
DEVICE ADDRESS (A
0
-
A
3
)
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input in
order to initiate communication with the X9258. A maximum
of 16 devices may occupy the 2-wire serial bus.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for the
DCP analog section.
Pin Names
SYMBOL
SCL
SDA
A0 thru A3
V
H0
/R
H0
thru V
H3
/R
H3
,
V
L0
/R
L0
thru V
L3
/R
L3
V
W0
/R
W0
thru V
W3
/R
W3
WP
V+, V-
V
CC
V
SS
NC
DESCRIPTION
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometers Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection (Allowed)
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
- V
L3
/R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
- V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Principles Of Operation
The X9258 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the DCP
potentiometers.
Serial Interface (2-Wire)
The X9258 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
FN8168.5
April 14, 2011
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
3
X9258
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9258 will be
considered a slave device in all applications.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier
(refer to Figure 1). For the X9258 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
LOW
). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
HIGH
). The X9258 continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
FIGURE 1. SLAVE ADDRESS
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8 bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8 bits of data.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte, the X9258 will
respond with a final acknowledge.
The next 4 bits of the slave address are the device address.
The physical device address is defined by the state of the A0
thru A3 inputs. The X9258 compares the serial data stream
with the address input state; a successful compare of all
4 address bits is required for the X9258 to respond with an
acknowledge. The A
0
thru A
3
inputs can be actively driven
by CMOS input signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs (during the internal nonvolatile
write operation), can be used to take advantage of the
typical 5ms nonvolatile write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile write
command, the X9258 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If the
X9258 is still busy with the write operation, no ACK will be
returned. If the X9258 has completed the write operation an
ACK will be returned and the master can then proceed with
the next operation.
Array Description
The X9258 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V
W
)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 8 bits of the WCR are
decoded to select, and enable, one of 256 switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated data
registers into the WCR. These data registers and the WCR
can be read and written by the host system.
4
FN8168.5
April 14, 2011
X9258
ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
.
REGISTER
SELECT
I3
I2
I1
I0
R1
R0
P1
P0
ISSUE
START
INSTRUCTIONS
WIPER COUNTER
REGISTER SELECT
FIGURE 2. INSTRUCTION BYTE FORMAT
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
RETURNED?
YES
NO
The four high order bits define the instruction. The next 2 bits
(R1 and R0) select one of the four registers that is to be
acted upon when a register oriented instruction is issued.
The last bits (P1, P0) select which one of the four
potentiometers is to be affected by the instruction.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the data
registers. A transfer from a Data Register to a Wiper Counter
Register is essentially a write to a static RAM. The response
of the wiper to this action will be delayed t
WRL
. A transfer
from the Wiper Counter Register (current wiper position), to
a data register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9258; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are: Read Wiper Counter Register (read
the current wiper position of the selected potentiometer),
Write Wiper Counter Register (change current wiper position
of the selected potentiometer), Read Data Register (read the
contents of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data register).
The sequence of operations is shown in Figure 4.
FURTHER
OPERATION?
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
Instruction Structure
The next byte sent to the X9258 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the two
potentiometers and when applicable they point to one of four
associated registers. The format is shown in Figure 2.
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1
P0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
5
FN8168.5
April 14, 2011
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