U4280BM
AM / FM - PLL
Description
The U4280BM is an integrated circuit in BICMOS
technology for frequency synthesizer. It performs all the
functions of a PLL radio tuning system and is controlled
by I
2
C bus. The device is designed for all frequency
synthesizer applications of radio receivers, as well as
RDS (Radio
Data System)
applications.
Features
D
Frequency range up to 150 MHz
D
Pre-amplifier for AM and FM
D
Fine tuning steps: AM 1kHz
D
Two programmable 16-bit divider,
adjustable from 2 to 65535
D
Reference oscillator up to 15 MHz
D
5 programmable switching outputs,
4 are open drain outputs up to 15 V
y
FM
y
2 kHz
D
Phase detector with separate outputs for AM and FM
D
Controlled via I
2
C bus
Ordering Information
Extended Type Number
U4280BM-B
U4280BM-BFL
Package
DIP20
SO20
Remarks
Block Diagram
PRT
OSCIN 18
19
OSCOUT
Latch
SCL
SDA
AS
2
Latch
3
4
I
2
C – BUS
interface
Shift register
Latch
Phase
detector
Current
sources
Status
14
15
13
12
AMOSC
Preamplifier
AM / FM–
switch
N – Divider
Analog
outputs
16
PDFM
PDAM
PDFMO
PDAMO
Oscillator
R – Divider
5
SWO1 SWO2 SWO3 AM/FM
6
7
8
9
Switching outputs
10
FMOSC
Preamplifier : 2
11
GND2
1
V
DD
20
GND1
Lock
detector
17
LD
13346
Figure 1. Block diagram
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
1 (9)
Preliminary Information
U4280BM
Pin Description
V
DD
SCL
1
2
20
GND
1
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
V
DD
SCL
SDA
AS
PRT
SWO1
SWO2
SWO3
AM/FM
FMOSC
GND2
AMOSC
PDFMO
PDFM
PDAM
PDAMO
LD
OSCIN
OSCOUT
GND1
Function
Supply voltage
I
2
C bus clock
I
2
C bus data
Address selection
Switching port
Switching output 1
Switching output 2
Switching output 3
Switching output AM/FM
FM oscillator input
Ground 2 (analog)
AM oscillator input
FM analog output
FM current output
AM current output
AM analog output
Lock detect
Oscillator input
Oscillator output
Ground 1 (digital)
19 OSCOUT
18 OSCIN
17 LD
16 PDAMO
15 PDAM
14 PDFM
13 PDFMO
12 AMOSC
11 GND
13319
SDA 3
AS
PRT
4
5
SWO1 6
SWO2 7
SWO3 8
AM/FM 9
FMOSC 10
Figure 2. Pinning
Functional Description
The U4280BM is controlled via the 2-wire I
2
C bus. For
programming there are one module address byte, two
subaddress bytes and five data bytes.
The module address contains a programmable address bit
A 1 which with address select input AS (Pin 4) makes it
possible to operate two U4280BM-B in one system. If bit
A 1 is identical with the status of the address select input
AS, the chip is selected.
The subaddress determines which one of the data bytes is
transmitted first. If subaddress of R-divider is
transmitted, the sequence of the next data bytes is DB 0
(Status), DB 1 and DB 2.
If subaddress of N-divider is transmitted, the sequence of
the next data bytes is DB 3 and DB 4. The bit organisation
of the module address, subaddress and 5 data bytes are
shown in figure 2
Each transmission on the I
2
C bus begins with the
“START ”-condition and has to be ended by the “STOP”-
condition (see figure 3).
The integrated circuit U 4283 BM has two separate inputs
for AM and FM oscillator. Pre-amplified AM signal is
directed to the 16 bit N-divider via AM/FM switch,
whereas (pre-amplified) FM signal is first divided by a
fixed prescaler ( :2 ). AM/FM switch is controlled by
software. Tuning steps can be selected by 16 bit
R-divider. Further there is a digital memory phase
detector. There are two separate current sources for AM
and FM amplifier (charge pump) as given in electrical
characteristics. It allows independent adjustment of gain,
whereby providing high current for high speed tuning and
low current for stable tuning.
2 (9)
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
U4280BM
Transmission Protocol
S
MSB
LSB
Address
A7
A0
A
Subaddress
R-divider
A
Data 0
A
Data 1
A
Data 2
A
P
S
MSB
LSB
Address
A7
A0
A
Subaddress
N-divider
A
Data 3
A
Data 4
A
A
P
S = Start
P = Stop
A = Acknowledge
Figure 4.
Absolute Maximum Ratings
Parameters
Supply voltage
Pin 1
Input voltages
Pins 2, 3, 4, 10, 12, 18 and 19
Output currents
Pins 3, 5, 6, 7, 8 and 9
Output drain voltage
Pins 6, 7, 8 and 9
Ambient temperature range
Storage temperature range
Symbol
V
DD
V
I
I
O
V
OD
T
amb
T
stg
Value
–0.3 to +6
–0.3 to V
DD
+ 0.3
–1 to +5
20
–25 to +85
–40 to +125
Unit
V
V
mA
V
°C
°C
Thermal Resistance
Parameters
Junction ambient
Symbol
R
thJA
Value
160
Unit
K/W
4 (9)
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
U4280BM
Electrical Characteristics
V
DD
= 5 V, T
amb
= 25°C, otherwise specified
Parameters
Supply voltage range
Quiescent supply voltage
FM input sensitivity
Test Conditions / Pins
Pin 1
Pin 1
R
G
= 50
W
Pin 10
f
i
= 30 to 60 MHz
f
i
= 70 to 120 MHz
f
i
= 120 to 130 MHz
R
G
= 50
W
Pin 12
f
i
= 0.4 to 35 MHz
R
G
= 50
W
Pin 18
f
i
= 0.1 to 15 MHz
Pin 5
I
H
= 1 mA
I
L
= 1 mA
I
L
= 0.1 mA
SWO1 to SWO3, AM/FM
(open drain outputs)
LD (open drain)
I
L
= 1 mA
Phase detector
PDFM
Output current 1
Output current 2
PDAM
Pin 15
Output current 1
Output current 2
Pins 14 and 15 to V
DD
Pins 14 and 15 to GND
H input voltage, Pins 2 and 3
L input voltage, Pins 2 and 3
I
SDAH
= 3 mA
Pin 2
I
O1
I
O2
I
13,16
I
13,16
V
IH
V
IL
V
O
f
SCL
t
r
t
f
t
H
t
L
t
wSTA
t
hSTA
t
sSTA
t
sDAT
t
hDAT
Pin 14
I
O1
I
O2
Pins 6 to 9
I
L
= 1 mA
I
L
= 0.1 mA
Pin 17
V
OL
±400
±100
±75
±20
0.1
3
0
0
±500
±125
±100
±25
–1
0.5
0.4
V
V
OL
V
OL
0.4
0.1
V
V
V
OH
V
OL
V
OL
V
DD
– 0.4
0.4
0.1
V
V
V
Symbol
V
DD
I
DD
V
I
V
i
V
i
V
i
V
i
Min.
4.5
Typ.
5.0
6.0
Max.
5.5
11.6
Unit
V
mA
mV
mV
mV
mV
mV
65535
50
25
50
25
100
2
AM input sensitivity
Oscillator input sensitivity
Adjustable divider
1)
Switching output, PRT
±600
±150
±100
±30
–2
V
DD
1.5
0.4
110
1
300
m
A
m
A
m
A
m
A
mA
mA
V
V
V
kHz
Analog output
I
2
bus inputs SCL, SDA
Output voltage
Clock frequency
Bus timing
Rise time SCL, SDA
Fall time SCL, SDA
“H” phase SCL
“L” phase SCL
Waiting time START
Set up time START
Set up time STOP
Set up time DATA
Hold time DATA
1)
m
s
ns
m
s
m
s
m
s
m
s
m
s
ns
m
s
4
4.7
4
4
4.7
250
0
FM input frequency is additionally divided by two (Pin 10).
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
5 (9)
Preliminary Information
MCU
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