S3C2501X
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
Revision 1
Important Notice
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any liability arising out of the application or use of any
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consequential or incidental damages.
S3C2501X RISC Microprocessor
User's Manual, Revision 1
Publication Number: 21-S3-C2501X-122002
© 2002 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
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"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
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Table of Contents
Chapter 1
Product Overview
1.1 Overview ...........................................................................................................................................1-1
1.2 Features ............................................................................................................................................1-2
1.3 Block Diagram ...................................................................................................................................1-4
1.4 Package Diagram ..............................................................................................................................1-5
1.5 Pin Assignment..................................................................................................................................1-6
1.6 Signal Description..............................................................................................................................1-12
1.7 Pad Type ...........................................................................................................................................1-26
1.8 Special Registers ...............................................................................................................................1-27
Chapter 2
Programmer's Model
2.1 Overview ...........................................................................................................................................2-1
2.2 Switching State ..................................................................................................................................2-1
2.2.1 Entering THUMB State ...........................................................................................................2-1
2.2.2 Entering ARM State................................................................................................................2-1
2.3 Memory Formats................................................................................................................................2-2
2.3.1 Big-Endian Format..................................................................................................................2-2
2.3.2 Little-Endian Format ...............................................................................................................2-2
2.4 Instruction Length ..............................................................................................................................2-3
2.5 Data Types ........................................................................................................................................2-3
2.6 Operating Modes ...............................................................................................................................2-3
2.7 Registers ...........................................................................................................................................2-4
2.7.3 The Relationship Between ARM and THUMB State Registers.................................................2-7
2.7.4 Accessing Hi-Registers in THUMB State.................................................................................2-8
2.8 The Program Status Registers ...........................................................................................................2-8
2.8.1 The Condition Code Flags ......................................................................................................2-9
2.8.2 The Control Bits......................................................................................................................2-9
2.9 Exceptions .........................................................................................................................................2-11
2.9.1 Action on Entering an Exception .............................................................................................2-11
2.9.2 Action on Leaving an Exception..............................................................................................2-11
2.9.3 Exception Entry/Exit Summary ...............................................................................................2-12
2.9.4 FIQ.........................................................................................................................................2-12
2.9.5 IRQ.........................................................................................................................................2-13
2.9.6 Abort ......................................................................................................................................2-13
2.9.7 Software Interrupt ...................................................................................................................2-14
2.9.8 Undefined Instruction..............................................................................................................2-14
2.10 Exception Vectors ............................................................................................................................2-14
2.10.1 Exception Priorities...............................................................................................................2-15
2.10.2 Not All Exceptions Can Occur at Once: ................................................................................2-15
2.11 Interrupt Latencies ...........................................................................................................................2-16
2.12 Reset ...............................................................................................................................................2-16
2.13 Introduction for ARM940T ................................................................................................................2-17
2.14 ARM940T Block Diagram.................................................................................................................2-18
2.15 About The ARM940T Programmer's Model ......................................................................................2-19
2.15.1 Data Abort Model..................................................................................................................2-20
2.15.2 Instruction Set Extension Spaces..........................................................................................2-20
2.16 ARM940T CP15 Registers ...............................................................................................................2-21
2.16.1 CP15 Register Map Summary ..............................................................................................2-21
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Table of Contents
(Continued)
Chapter 3
Instruction Set
3.1 Instruction Set Summay .................................................................................................................... 3-1
3.1.1 Format Summary................................................................................................................... 3-1
3.1.2 Instruction Summary.............................................................................................................. 3-2
3.2 The Condition Field........................................................................................................................... 3-4
3.3 Branch and Exchange (BX) ............................................................................................................... 3-5
3.3.1 Instruction Cycle Times.......................................................................................................... 3-5
3.3.2 Assembler Syntax.................................................................................................................. 3-5
3.3.3 Using R15 as an Operand...................................................................................................... 3-5
3.4 Branch and Branch with Link (B, BL) ................................................................................................. 3-7
3.4.1 The Link Bit ........................................................................................................................... 3-7
3.4.2 Instruction Cycle Times.......................................................................................................... 3-7
3.4.3 Assembler Syntax.................................................................................................................. 3-8
3.5 Data Processing................................................................................................................................ 3-9
3.5.1 CPSR Flags........................................................................................................................... 3-11
3.5.2 Shifts ..................................................................................................................................... 3-12
3.5.3 Immediate Operand Rotates .................................................................................................. 3-16
3.5.4 Writing to R15........................................................................................................................ 3-16
3.5.5 Using R15 as an Operand...................................................................................................... 3-16
3.5.6 Teq, Tst, Cmp and CMN Opcodes ......................................................................................... 3-16
3.5.7 Instruction Cycle Times.......................................................................................................... 3-17
3.6.8 Assembler Syntax.................................................................................................................. 3-17
3.6 PSR Transfer (MRS, MSR) ............................................................................................................... 3-19
3.6.1 Operand Restrictions ............................................................................................................. 3-19
3.6.2 Reserved Bits ........................................................................................................................ 3-21
3.6.3 Instruction Cycle Times.......................................................................................................... 3-21
3.6.4 Assembler Syntax.................................................................................................................. 3-22
3.7 Multiply and Multiply-Accumulate (MUL, MLA) .................................................................................. 3-23
3.7.1 CPSR Flags........................................................................................................................... 3-24
3.7.2 Instruction Cycle Times.......................................................................................................... 3-24
3.7.3 Assembler Syntax.................................................................................................................. 3-24
3.8 Multiply Long and Multiply-Accumulate Long (MULL, MLAL) ............................................................. 3-25
3.8.1 Operand Restrictions ............................................................................................................. 3-25
3.8.2 CPSR Flags........................................................................................................................... 3-26
3.8.3 Instruction Cycle Times.......................................................................................................... 3-26
3.8.4 Assembler Syntax.................................................................................................................. 3-27
3.9 Single Data Transfer (LDR, STR)...................................................................................................... 3-28
3.9.1 Offsets and Auto-Indexing ..................................................................................................... 3-29
3.9.2 Shifted Register Offset........................................................................................................... 3-29
3.9.3 Bytes and Words ................................................................................................................... 3-29
3.9.4 Use of R15............................................................................................................................. 3-31
3.9.5 Restriction on the Use of Base Register ................................................................................. 3-31
3.9.6 Data Aborts............................................................................................................................ 3-31
3.9.7 Instruction Cycle Times.......................................................................................................... 3-31
3.9.8 Assembler Syntax.................................................................................................................. 3-32
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Table of Contents
(Continued)
Chapter 3
Instruction Set
(Continued)
3.10 Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH).................................................3-34
3.10.1 Offsets and Auto-Indexing ....................................................................................................3-35
3.10.2 Half-Word Load and Stores ..................................................................................................3-36
3.10.3 Signed Byte and Half-Word Loads ........................................................................................3-36
3.10.4 Endianness and Byte/Half-Word Selection............................................................................3-36
3.10.5 Use of R15 ...........................................................................................................................3-37
3.10.6 Data Aborts...........................................................................................................................3-37
3.10.7 Instruction Cycle Times ........................................................................................................3-37
3.10.8 Assembler Syntax.................................................................................................................3-38
3.11 Block Data Transfer (LDM, STM) .....................................................................................................3-40
3.11.1 The Register List...................................................................................................................3-40
3.11.2 Addressing Modes ................................................................................................................3-41
3.11.3 Address Alignment................................................................................................................3-41
3.11.4 Use of the S Bit ....................................................................................................................3-43
3.11.5 Use of R15 as the Base ........................................................................................................3-43
3.11.6 Inclusion of the Base in the Register List...............................................................................3-44
3.11.7 Data Aborts...........................................................................................................................3-44
3.11.8 Instruction Cycle Times ........................................................................................................3-44
3.11.9 Assembler Syntax.................................................................................................................3-45
3.12 Single Data Swap (SWP) .................................................................................................................3-47
3.12.1 Bytes and Words ..................................................................................................................3-47
3.12.2 Use of R15 ...........................................................................................................................3-47
3.12.3 Data Aborts...........................................................................................................................3-48
3.12.4 Instruction Cycle Times ........................................................................................................3-48
3.12.5 Assembler Syntax.................................................................................................................3-48
3.13 Software Interrupt (SWI) ..................................................................................................................3-49
3.13.1 Return from the Supervisor...................................................................................................3-49
3.13.2 Comment Field .....................................................................................................................3-49
3.13.3 Instruction Cycle Times ........................................................................................................3-49
3.13.4 Assembler Syntax.................................................................................................................3-50
3.14 Coprocessor Data Operations (CDP)................................................................................................3-51
3.14.1 Coprocessor Instructions.......................................................................................................3-51
3.14.2 The Coprocessor Fields ........................................................................................................3-51
3.14.3 Instruction Cycle Times ........................................................................................................3-52
3.14.4 Assembler Syntax.................................................................................................................3-52
3.15 Coprocessor Data Transfers (LDC, STC) .........................................................................................3-53
3.15.1 The Coprocessor Fields ........................................................................................................3-53
3.15.2 Addressing Modes ................................................................................................................3-54
3.15.3 Address Alignment................................................................................................................3-54
3.15.4 Use of R15 ...........................................................................................................................3-54
3.15.5 Data Aborts...........................................................................................................................3-54
3.15.6 Instruction Cycle Times ........................................................................................................3-54
3.15.7 Assembler Syntax.................................................................................................................3-55
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