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RD09MUP2_10

Description
RoHS Compliance, Silicon MOSFET Power Transistor, 520MHz, 8W
File Size141KB,8 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
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RD09MUP2_10 Overview

RoHS Compliance, Silicon MOSFET Power Transistor, 520MHz, 8W

Silicon RF Power Semiconductors
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
RD09MUP2
(a)
0.2+/-0.05
8.0+/-0.2
0.65+/-0.2
(c)
(b)
7.0+/-0.2
(b)
6.2+/-0.2
5.6+/-0.2
4.2+/-0.2
RoHS Compliance, Silicon MOSFET Power Transistor, 520MHz, 8W
DESCRIPTION
RD09MUP2 is a MOS FET type transistor
specifically designed for UHF RF power
amplifiers applications.
(3.6)
(d)
FEATURES
•High power gain:
Pout>8W, Gp>10dB@Vdd=7.2V,f=520MHz
(4.5)
0.95+/-0.2
2.6+/-0.2
•High Efficiency: 50%min. (520MHz)
•Integrated gate protection diode
INDEX MARK
[Gate]
TOP VIEW
DETAIL A
SIDE VIEW
1.8+/-0.1
BOTTOM VIEW
Terminal No.
(a)Drain [output]
(b)Source [GND]
(c)Gate [input]
(d)Source
APPLICATION
SIDE VIEW
Standoff = max 0.05
For output stage of high power amplifiers in
UHF band mobile radio sets.
0.7+/-0.1
UNIT:mm
DETAIL A
NOTES:
1. ( ) Typical value
RoHS COMPLIANT
RD09MUP2 is a RoHS compliant product.
RoHS compliance is indicating by the letter “G” after the Lot Marking. This product includes the lead in high
melting temperature type solders. However, it is applicable to the following exceptions of RoHS Directions.
1.Lead in high melting temperature type solders (i.e. tin-lead older alloys containing more than85% lead.)
ABSOLUTE MAXIMUM RATINGS
(Tc=25
°C
UNLESS OTHERWISE NOTED)
SYMBOL
VDSS
VGSS
ID
Pin
Pch
Tj
Tstg
Rth j-c
PARAMETER
Drain to source voltage
Gate to source voltage
Drain Current
Input Power
Channel dissipation
Junction Temperature
Storage temperature
Thermal resistance
CONDITIONS
Vgs=0V
Vds=0V
-
Zg=Zl=50
Tc=25
°C
-
-
Junction to case
RATINGS
40
-5 to +10
4.0
1.6
83
150
-40 to +125
1.5
UNIT
V
V
A
W
W
°C
°C
°C/W
D
G
S
SCHEMATIC DRAWING
Note: Above parameters are guaranteed independently.
ELECTRICAL CHARACTERISTICS
(Tc=25
°C
, UNLESS OTHERWISE NOTED)
SYMBOL
I
DSS
I
GSS
V
TH
Pout
ηD
PARAMETER
Zero gate voltage drain current
Gate to source leak current
Gate threshold Voltage
Output power
Drain efficiency
CONDITIONS
V
DS
=17V, V
GS
=0V
V
GS
=10V, V
DS
=0V
V
DS
=12V, I
DS
=1mA
f=520MHz , V
DD
=7.2V
Pin=0.8W,Idq=1.0A
V
DD
=9.5V,Po=8W(Pin Control)
f=520MHz,Idq=1.0A,Zg=50
Load VSWR=20:1(All Phase)
MIN
-
-
0.5
8
50
LIMITS
TYP
MAX.
-
10
-
1
-
2.5
9
-
-
-
No destroy
UNIT
uA
uA
V
W
%
-
VSWRT Load VSWR tolerance
Note: Above parameters, ratings, limits and conditions are subject to change.
RD09MUP2
17 Aug 2010
1/8

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