UNISONIC TECHNOLOGIES CO., LTD
UR5512
2A DDR BUS TERMINATION
REGULATOR
SOP-8
LINEAR INTEGRATED CIRCUIT
DESCRIPTION
The UTC
UR5512
is a linear regulator which provides up to 2
Amp bi-directional driving and sinking capability for DDR SDRAM
bus terminator application. The output termination voltage tracks the
reference voltage applied at V
REF
pin. A resistor divider connected to
V
IN
, GND and V
REF
pins is used to force a reference voltage to V
REF
pin.
The UTC
UR5512
contains a high-speed operational amplifier to
provide excellent response to line/load transient. An active-low
shutdown (V
REF
) pin provides Suspend to RAM (STR) functionality.
Additional features include current limiting protection, on-chip
thermal shut-down protection.
HSOP-8
1
TO-252-5
FEATURES
* DDR-I and DDR-II termination voltage applications
* Driving and sinking current up to 2A
* Low output voltage offset (within 20mV@±2A)
* Adjustable output voltage by external resistors
* Suspend to RAM (STR) functionality
* Current limiting protection
* Thermal protection
*
Cost-effective and
easy to use
Lead-free:
UR5512L
Halogen-free: UR5512G
ORDERING INFORMATION
Normal
UR5512-S08-R
UR5512-SH2-R
UR5512-TN5-R
Ordering Number
Lead Free Plating
UR5512L-S08-R
UR5512L-SH2-R
UR5512L-TN5-R
Halogen Free
UR5512G-S08-R
UR5512G-SH2-R
UR5512G-TN5-R
Package
SOP-8
HSOP-8
TO-252-5
Packing
Tape Reel
Tape Reel
Tape Reel
UR5512L-S08-R
(1)Packing Type
(2)Package Type
(3)Lead Plating
(1) R: Tape Reel
(2) S08: SOP-8, SH2: HSOP-8, TN5: TO-252-5
(3) G: Halogen Free, L: Lead Free, Blank: Pb/Sn
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QW-R101-017,D
UR5512
ABSOLUTE MAXIMUM RATINGS
PARAMETER
LINEAR INTEGRATED CIRCUIT
SYMBOL
RATING
UNIT
V
CNTL
Control Voltage
V
CNTL
-0.2 ~ 7
V
V
IN
Supply Voltage
V
IN
-0.2 ~ 6
V
Power Dissipation
P
D
Internally Limited
W
Junction Temperature
T
J
+125
°C
Storage Temperature
T
STG
-40 ~ +150
°C
Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Note:
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
RANGE
V
CNTL
Control Voltage (Note 1)
V
CNTL
3.1 ~ 6
V
IN
Supply Voltage
V
IN
1.6 ~ 5.5
V
REF
Input Voltage
V
REF
0.85 ~ 1.75
V
OUT
Output Voltage (Note 2)
V
OUT
V
REF
± 0.02
V
OUT
Output Current
I
OUT
-2 ~ +2
Junction Temperature
T
J
0 ~ +125
Notes: 1. Please always keep V
CNTL
-V
OUT
>1.9V
for good regulation.
2. The V
OUT
tracks the V
REF
with additional voltage offset and load regulation.
UNIT
V
V
V
V
A
°C
ELECTRICAL CHARACTERISTICS
(V
IN
= 1.8V, V
CNTL
= 5V, V
REFEN
= 0.5V
IN
), Ta = 25°C, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
INPUT CURRENT
I
OUT
= 0A
Operation Current of V
CNTL
I
CNTL
V
REF
=GND (Shutdown)
V
REF
=1.25V
Current into V
REF
Pin
I
REF
V
REF
= GND (Shutdown)
Standby Current
I
STB
V
REF
< 0.2V, R
LOAD
= 180Ω
OUTPUT VOLTAGE
Output Voltage Offset (V
OUT
- V
REF
)
V
O(OFF)
I
OUT
= 0A
Load Regulation
ΔV
LOAD
I
OUT
= ±1.5A
PROTECTION
Current limit
I
LIMIT
Thermal Shutdown Temperature
T
SD
V
CNTL
= 5V
Thermal Shutdown Hysteresis
ΔT
SD
V
CNTL
= 5V
REFEN Shutdown
V
IH
Enable
Shutdown Threshold
V
IL
Shutdown
MIN
TYP
2
1.9
200
20
50
-20
-20
2.0
125
6
MAX
4
500
40
90
+20
+20
UNIT
mA
mA
nA
µA
µA
mV
mV
A
°C
°C
V
V
180
40
0.6
0.15
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QW-R101-017,D
UR5512
FUNCTIONAL DESCRIPTION
LINEAR INTEGRATED CIRCUIT
General Information
The UTC
UR5512
is a linear regulator designed for DDR SDRAM bus terminator application. The output, V
OUT
is
capable of sourcing or sinking current up to 2A peak while regulating the output voltage to within 20mV offset. The
UTC
UR5512
has excellent response to load regulation while preventing shoot through. Active-low shutdown
mechanism and fault protections. The UTC
UR5512
is available in several packages to meet different power
dissipation and surface mount applications.
Output Voltage Regulation
The output voltage tracks the reference voltage applied at V
REF
pin. Two internal NPN pass transistors act as
the buffered output regulate the output voltage by sourcing current from V
IN
pin or sinking current to GND pin. An
internal Kelvin sensing scheme is use at the V
OUT
pin to improve load regulation at various load current. Since the
UTC
UR5512
exhibits excellent response to load transient, lesser amount of capacitors can be used.
Current Limit
An internal current limiting sensor is used to monitor the maximum output current to prevent damages from
overload or short-circuit condition. Increasing the input voltage of V
IN
or V
CNTL
will get higher current-limit points.
Shutdown and Soft-Start
An additional function of the V
REF
pin is acting as a shutdown control input that can be used for
suspend to RAM
functionality.
Applying and holding a voltage below 0.15V to V
REF
pin shuts down the output of the regulator. An
external NPN transistor or N-channel MOSFET is used to pull down the V
REF
pin voltage; while applying a “high”
signal to turn on the transistor. During shutdown condition, the two pass transistors are turned off and the output
V
OUT
will tri-state; sourcing or sinking no current. When releasing the V
REF
pin, the current through the resistor
divider charges the capacitor Css to initiate a soft-start cycle.
Thermal Shutdown
If the junction temperature exceeds the thermal shutdown (T
J
= +150°C) then the part will enter a shutdown state.
A thermal sensor turns off both pass transistors, allowing the device to cool down. After the junction temperature
reduces by 40°C, the regulator starts to regulate again; resulting in a pulsed output during continuous thermal
overload conditions.
Power Inputs
Input powers up sequence are not required for V
IN
and V
CNTL
. Be careful; do not apply voltage to V
OUT
when there
is no V
CNTL
voltage presented. This is due to the internal parasitic diodes between V
OUT
to V
IN
and V
OUT
to V
CNTL
which will be forward bias.
Reference Voltage
The reference voltage is programmed by a resistor divider between V
IN
and GND pins. The recommended resistor
is < 5kΩ to maintain the accuracy of the output voltage. For improved the performance, an external bypass capacitor
can be used, located close to V
REF
pin to help with noise. A ceramic capacitor can be use and is selected to be
greater than 0.1μF. Do not place any additional loading on this reference input pin.
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www.unisonic.com.tw
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QW-R101-017,D
FPGA/CPLD
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