GS8642Z18/36/72(B/C)-xxxV
119- & 209-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- or 209-bump BGA package
• RoHS-compliant 119- and 209-bump BGA packages
available
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–167 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8642Z18/36/72(B/C)-xxxV may be configured by the
user to operate in Pipeline or Flow Through mode. Operating
as a pipelined synchronous device, in addition to the rising-
edge-triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
Functional Description
The GS8642Z18/36/72(B/C)-xxxV is a 72Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
The GS8642Z18/36/72(B/C)-xxxV is implemented with GSI's
or other pipelined read/double late write or flow through read/
high performance CMOS technology and is available in a
single late write SRAMs, allow utilization of all available bus
JEDEC-standard 119-bump or 209-bump BGA package.
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
3.0
4.0
340
410
520
6.5
6.5
245
280
370
-200
3.0
5.0
290
350
435
7.5
7.5
220
250
315
-167
3.4
6.0
260
305
380
8.0
8.0
210
240
300
Unit
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
Flow Through
2-1-1-1
Rev: 1.04a 2/2009
1/33
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8642Z18/36/72(B/C)-xxxV
GS8642Z72C-xxxV 209-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
B
A
, B
B
B
C
,B
D
B
E
, B
F
, B
G
,B
H
NC
CK
E
1
E
3
E
2
G
ADV
ZZ
FT
LBO
MCH
MCH
MCL
W
ZQ
CKE
I
I
I
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I/O
Data Input and Output pins
I
I
I
—
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
No Connect
Clock Input Signal; active high
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect High
Must Connect Low
Write Enable; active low
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]
Clock Enable; active low
Rev: 1.04a 2/2009
3/33
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
京公网安备 11010802033920号
EEWORLD
