IS61NLP51236B-250B3LA3 datasheet, PDF

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IS61NLP51236B-250B3LA3: DescriptionStandard SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, TFBGA-165; Categorystorage storage; File Size2MB，39 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61NLP51236B-250B3LA3 Overview

Standard SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, TFBGA-165

IS61NLP51236B-250B3LA3 Parametric

Parameter Name	Attribute value
Maker	Integrated Silicon Solution ( ISSI )
package instruction	TBGA,
Reach Compliance Code	unknown
Maximum access time	2.6 ns
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B

IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B

512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS

SYNCHRONOUS SRAM

FEBRUARY 2014

ADVANCED INFORMATION

FEATURES

•

100 percent bus utilization

•

No wait cycles between Read and Write

•

Internal self-timed write cycle

•

Individual Byte Write Control

•

Single R/W (Read/Write) control pin

•

Clock controlled, registered address, data and

control

•

Interleaved or linear burst sequence control

using MODE input

•

Three chip enables for simple depth

expansion and address pipelining

•

Power Down mode

•

Common data inputs and data outputs

•

/CKE pin to enable clock and suspend

operation

•

JEDEC 100-pin QFP, 165-ball BGA and 119-

ball BGA packages

•

Power supply:

NLP: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

NVP: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

NVVP: V

1.8V (± 5%), V

DDQ

1.8V (± 5%)

•

JTAG Boundary Scan for BGA packages

•

Commercial, Industrial and Automotive (x36)

temperature support

•

Lead-free available

•

For leaded option, please contact ISSI.

DESCRIPTION

The 18Meg product family features high-speed,

low-power synchronous static RAMs designed to

provide a burstable, high-performance, 'no wait'

state, device for networking and communications

applications. They are organized as 512K words

by 36 bits and 1024K words by 18 bits, fabricated

with

ISSI's

advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles

are eliminated when the bus switches from read

to write, or write to read. This device integrates a

2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single

monolithic circuit.

All synchronous inputs pass through registers are

controlled by a positive-edge-triggered single

clock input. Operations may be suspended and all

synchronous inputs ignored when Clock Enable,

/CKE is HIGH. In this state the internal device will

hold their previous values.

All Read, Write and Deselect cycles are initiated

by the ADV input. When the ADV is HIGH the

internal burst counter is incremented. New

external addresses can be loaded when ADV is

LOW.

Write cycles are internally self-timed and are

initiated by the rising edge of the clock inputs and

when /WE is LOW. Separate byte enables allow

individual bytes to be written.

A burst mode pin (MODE) defines the order of the

burst sequence. When tied HIGH, the interleaved

burst sequence is selected. When tied LOW, the

linear burst sequence is selected.

FAST ACCESS TIME

Symbol

tKQ

tKC

Parameter

Clock Access Time

Cycle time

Frequency

-250

2.6

250

-200

3.0

200

Units

MHz

any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.

Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders

for products.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

2/13/2014

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