5SGSMD6K2F40C2 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> 5SGSMD6K2F40C2

5SGSMD6K2F40C2: DescriptionField Programmable Gate Array, 583000-Cell, CMOS, PBGA1517,; CategoryProgrammable logic devices Programmable logic; File Size388KB，22 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric View All

5SGSMD6K2F40C2 Overview

Field Programmable Gate Array, 583000-Cell, CMOS, PBGA1517,

5SGSMD6K2F40C2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B1517
Number of entries	696
Number of logical units	583000
Output times	696
Number of terminals	1517
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1517,39X39,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	0.9,1.5,2.5,2.5/3,1.2/3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM

Preview

Download Datasheet

View All

1. Stratix V Device Family Overview

February 2012

SV51001-2.3

This chapter provides an overview of the Stratix

V devices and their features. Many

of these devices and features are enabled in the Quartus

II software version 11.1. The

remaining devices and features will be enabled in future versions of the Quartus II

software.

To find out more about the upcoming Stratix V devices and features, refer to the

Stratix V Upcoming Device Features

document.

Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core

architecture, integrated transceivers up to 28.05 gigabits per second (Gbps), and a

unique array of integrated hard intellectual property (IP) blocks. With these

innovations, Stratix V FPGAs deliver a new class of application-targeted devices

optimized for:

■

Bandwidth-centric applications and protocols, including PCI Express

(PCIe

)

Gen3

Data-intensive applications for 40G/100G and beyond

High-performance, high-precision digital signal processing (DSP) applications

■

Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a

different set of applications. For higher volume production, you can prototype with

Stratix V FPGAs and use the low-risk, low-cost path to HardCopy

V ASICs.

Stratix V Family Variants

Stratix V GT

devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are

optimized for applications that require ultra-high bandwidth and performance in

areas such as 40G/100G/400G optical communications systems and optical test

systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX

channels, respectively.

Stratix V GX

devices offer up to 66 integrated 14.1-Gbps transceivers supporting

backplanes and optical modules. These devices are optimized for high-performance,

high-bandwidth applications such as 40G/100G optical transport, packet processing,

and traffic management found in wireline, military communications, and network

test equipment markets.

Stratix V GS

devices have an abundance of variable precision DSP blocks, supporting

up to 3,926 18x18 or 1,963 27x27 multipliers. In addition, Stratix V GS devices offer

integrated 14.1-Gbps transceivers, which support backplanes and optical modules.

These devices are optimized for transceiver-based DSP-centric applications found in

wireline, military, broadcast, and high-performance computing markets.

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Stratix V Device Handbook

Volume 1: Overview and Datasheet

February 2012

Recommended Resources

Control circuit a for one of the two motors to start first and then stop

Motor automatic mutual switching circuit controlled by transfer switch a

A,D conversion circuit diagram

Logarithmic amplifier circuit

Fishing game circuit

TDA2003NEW power amplifier circuit

200 free shipping Qingfeng QF-TM4C123 TI LM4F232 Cortex-M4 development board: [i=s]This post was last edited by nwcheroes on 2014-8-4 09:52[/i] [size=4]Qingfeng QF-TM4C123 development board, used for a while when doing graduation project, then left it to collect dust. Now it is...; nwcheroes Buy&Sell

PIC16F54 key scan has no response: I used PIC16F54 to make a program to switch the digital tube display by key scanning. The digital tube is driven by 74HC164. The display program has been tested and each page can be displayed normally...; 木瓜舟舟 Microchip MCU

【TI original】Software decoding of quadrature encoder: The quadrature encoder, a type of rotary encoder (incremental encoder), is used to determine the displacement and direction of the mechanical stroke. By monitoring the number of pulses and the relativ...; 柳叶舟 Microcontroller MCU

This week's highlights: [b][url=http://www.deyisupport.com/blog/b/the_process/archive/2016/04/06/66ak2l06-soc.aspx][b]Can the 66AK2L06 SoC enable the minimization of test and measurement equipment? [/b][/url][/b] [b][/b] [al...; 橙色凯 DSP and ARM Processors

What are the DSPs used for image processing?: Do you know what DSP chips are commonly used for image processing? I hope you can give me some advice, haha...; fujianfeng Embedded System

at tiny44a simply use the ad conversion, but the conversion completion flag is not set: I use atmel studio6.0 with a main frequency of 8M. Every time I reach while, it stops. /* * ADC.c * * Created: 2012/6/18 16:13:15 * Author: Administrator */ #include #includeunsigned int Adc_Val; unsi...; 07031529 Microchip MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components