82807AAVCH datasheet, PDF - EEWORLD Datasheet

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82807AAVCH: DescriptionConsumer Circuit, PBGA196, PLASTIC, BGA-196; CategoryOther integrated circuit (IC) Consumption circuit; File Size665KB，88 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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82807AAVCH Overview

Consumer Circuit, PBGA196, PLASTIC, BGA-196

82807AAVCH Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	BGA
package instruction	BGA,
Contacts	196
Reach Compliance Code	unknown
Commercial integrated circuit types	CONSUMER CIRCUIT
JESD-30 code	S-PBGA-B196
length	15 mm
Number of functions	1
Number of terminals	196
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum slew rate	610.2 mA
Maximum supply voltage (Vsup)	1.89 V
Minimum supply voltage (Vsup)	1.71 V
surface mount	YES
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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Intel 82807AA Video Controller Hub

(VCH)

Datasheet

October 2000

Document Reference Number:

290690-001

82807AA VCH

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness

for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in

medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future

definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

82807AA VCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. Implementations

of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

www.intel.com

or call 1-800-548-4725

*Third-party brands and names are the property of their respective owners.

Datasheet

82807AA VCH

Contents

Introduction .................................................................................................................................. 9

Product Features........................................................................................................................ 11

Pin Description ........................................................................................................................... 16

3.1.

3.2.

3.3.

3.4.

3.5.

3.6.

3.7.

3.8.

3.9.

3.10.

3.11.

4.1.

Notation ......................................................................................................................... 16

DVO Interface Signals ................................................................................................... 16

DVOr Interface Signals.................................................................................................. 17

CMOS LCD Interface Signals........................................................................................ 17

LVDS LCD Interface Signals ......................................................................................... 18

GMBus Signals.............................................................................................................. 18

PLL ................................................................................................................................ 19

GP I/O Signals............................................................................................................... 19

Mvssiscellaneous Signals.............................................................................................. 19

82807AA VCH Core Power and Ground ....................................................................... 20

Pin States ...................................................................................................................... 21

DVO to 82807AA VCH .................................................................................................. 23

4.1.1.

Connection .................................................................................................. 23

4.1.2.

DVO Data Format ....................................................................................... 24

4.1.3.

Timing Controls ........................................................................................... 26

4.1.4.

Differential Clocking .................................................................................... 27

4.1.5.

Stalling ........................................................................................................ 27

DVOr Interface .............................................................................................................. 28

LVDS LCD Interface...................................................................................................... 28

4.3.1.

Clock Pair .................................................................................................... 29

4.3.2.

Data Pair ..................................................................................................... 29

82807AA VCH LCD Display Modes .............................................................................. 31

5.1.1.

Normal Mode............................................................................................... 31

5.1.2.

82815EM Centering .................................................................................... 31

5.1.3.

82815EM Panning....................................................................................... 31

5.1.4.

Panel-fitting Mode ....................................................................................... 32

5.1.5.

DVO Bypass Mode...................................................................................... 32

GMBus Interface ........................................................................................................... 33

5.2.1.

Base Address .............................................................................................. 33

5.2.2.

Index Address ............................................................................................. 33

5.2.3.

Transfer Format .......................................................................................... 34

Register Description ...................................................................................................... 35

6.1.1.

Header ........................................................................................................ 35

6.1.1.1.

VR00 – 82807AA VCH Revision and GMbus Base Address ......... 35

6.1.1.2.

VR01 – 82807AA VCH Functionality Enable .................................. 36

6.1.2.

LCD Interfaces ............................................................................................ 37

Interface Description .................................................................................................................. 23

4.2.

4.3.

82807AA VCH Basic Operation ................................................................................................. 31

5.1.

5.2.

Register Description................................................................................................................... 35

6.1.

Datasheet

82807AA VCH

6.1.3.

6.1.4.

6.1.5.

6.1.6.

6.1.7.

6.1.8.

6.1.2.1.

VR10 – LCD Interface Format ........................................................37

6.1.2.2.

VR11 – CMOS Output Control ........................................................38

6.1.2.3.

VR12 – LVDS Output Control .........................................................39

PLL

........................................................................................................39

6.1.3.1.

VR18 – PLL clock select .................................................................40

6.1.3.2.

VR19 – PLL clock divisor ................................................................40

6.1.3.3.

VR1A – PLL clock divisor................................................................40

Flat Panel Timing.........................................................................................41

6.1.4.1.

VR22 – Horizontal TRP to DE Start Delay ......................................41

6.1.4.2.

VR23 – Horizontal TRP to DE End Delay .......................................41

6.1.4.3.

VR24 – Horizontal TRP to LP Start Delay.......................................41

6.1.4.4.

VR25 – Horizontal TRP to LP End Delay ........................................41

6.1.4.5.

VR26 – Vertical TRP to FLM Start Delay ........................................42

6.1.4.6.

VR27 – Vertical TRP to FLM End Delay .........................................42

Power Sequencing and Panel Protection ....................................................43

6.1.5.1.

VR30 – Panel Power Shut Down Status .........................................43

6.1.5.2.

VR31 – Tpon Panel Power-on Sequencing Delay ..........................43

6.1.5.3.

VR32 – Tpoff Panel Power-off Sequencing Delay .........................44

6.1.5.4.

VR33 – Tstay Panel Power-off Stay Down Delay ..........................44

6.1.5.5.

VR34 – Maximum FLM Pulse Interval ............................................45

6.1.5.6.

VR35 – Maximum LP Pulse Interval ...............................................45

Panel Fitting .................................................................................................46

6.1.6.1.

VR40 – Panel Fitting Controls .........................................................46

GPIO ........................................................................................................47

6.1.7.1.

VR80 – GPIO0 Control....................................................................47

6.1.7.2.

VR81 – GPIO1 Control....................................................................47

6.1.7.3.

VR82 – GPIO 2 Control...................................................................48

6.1.7.4.

VR83 – GPIO 3 Control...................................................................48

6.1.7.5.

VR84 – GPIO 4 Control...................................................................48

6.1.7.6.

VR85 – GPIO 5 Control...................................................................49

6.1.7.7.

VR86 – GPIO 6 Control...................................................................50

6.1.7.8.

VR87 – GPIO 7 Control...................................................................51

6.1.7.9.

VR88 – GPIO 8 Control...................................................................51

Graphics BIOS Scratch Space ....................................................................52

6.1.8.1.

VR8E – Video BIOS Scratch Register 0 .........................................52

6.1.8.2.

VR8F – Video BIOS Scratch Register 1..........................................52

Functional Description ................................................................................................................53

7.1.

Timing Control................................................................................................................53

7.1.1.

Timing Reference Point Generation ............................................................53

7.1.1.1.

Flat Panel Timing Diagram .............................................................53

Up Scaling......................................................................................................................55

7.2.1.

Scaling Algorithm .........................................................................................55

7.2.1.1.

Bi-Linear Interpolation .....................................................................55

7.2.1.2.

Multiple Segmented High Order Curve Interpolation ......................56

LVDS Transmitter ..........................................................................................................56

7.3.1.

PLL

........................................................................................................56

7.3.1.1.

Serializer With Control ....................................................................56

Panel Protection and Power Sequencing.......................................................................57

7.4.1.

Panel Protection...........................................................................................57

7.4.1.1.

Panel Power Sequencing ................................................................57

DVO Bypassing..............................................................................................................57

7.5.1.

DVOrRCOM.................................................................................................58

7.5.2.

DVO to DVOr Electrical Isolation .................................................................58

7.2.

7.3.

7.4.

7.5.

Datasheet

82807AA VCH

7.6.

7.5.3.

Spread-Spectrum Clocking Support............................................................ 58

Power Supply................................................................................................................. 58

7.6.1.

System Connection ..................................................................................... 58

82807AA VCH Pinout .................................................................................................... 61

Physical Dimensions ..................................................................................................... 66

Related Documents and References ............................................................................ 69

Electrical Characteristics ............................................................................................... 69

9.2.1.

Absolute Maximum DC Ratings .................................................................. 69

9.2.2.

Signal Groups.............................................................................................. 70

9.2.3.

DC Characteristics ...................................................................................... 71

9.2.4.

Ac Characteristics ....................................................................................... 72

9.2.4.1.

Phase Lock Loop Clock Input Timing............................................ 72

9.2.4.2.

Digital Video Out(DVO) Port Interface Timing ................................ 72

9.2.5.

82807AA VCH LVDS Switching Characteristics ......................................... 75

9.2.5.1.

CMOS LCD Panel Interface Timing............................................... 76

82807AA VCH Timing Diagrams................................................................................... 76

9.3.1.

82807AA VCH LVDS Timing Diagrams ...................................................... 78

Power/Thermal Characteristics ..................................................................................... 80

9.4.1.

Power Characteristics ................................................................................. 80

9.4.2.

Thermal Management Introduction ............................................................. 80

9.4.3.

Importance of Thermal Management.......................................................... 80

9.4.3.1.

Thermal Specifications ................................................................... 81

9.4.3.2.

Case Temperature.......................................................................... 81

9.4.3.3.

Measurements for Thermal Specifications ..................................... 81

9.4.3.4.

Case Temperature Measurements................................................. 81

CMOS LCD Interface Pixel Data Mapping .................................................................... 83

LVDS LCD Interface Pixel Data Serial Mapping............................................................ 84

Pinout and Package Information ................................................................................................ 61

8.1.

8.2.

External Timing Specifications ................................................................................................... 68

9.1.

9.2.

9.3.

9.4.

10.

Appendix .................................................................................................................................... 83

10.1.

10.2.

Datasheet

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