64-bit Intel
®
Xeon™ Processor
MP with up to 8MB L3 Cache
Datasheet
March 2005
Document Number:
306754-001
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ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 64-Bit Intel
®
Xeon™ processor MP with up to 8MB L3 cache may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Intel, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
2
64-bit Intel
®
Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
Contents
1
Introduction....................................................................................................................... 11
1.1
1.2
1.3
2
2.1
Terminology......................................................................................................... 12
References .......................................................................................................... 14
State of Data ....................................................................................................... 15
Front Side Bus and GTLREF .............................................................................. 17
2.1.1 Front Side Bus Clock and Processor Clocking....................................... 18
2.1.2 Front Side Bus Clock Select (BSEL[1:0]) ............................................... 19
2.1.3 Phase Lock Loop (PLL) Power and Filter............................................... 19
Voltage Identification (VID).................................................................................. 20
Cache Voltage Identification (CVID).................................................................... 23
Reserved, Unused, and TESTHI Pins.................................................................24
Mixing Processors ............................................................................................... 24
Front Side Bus Signal Groups............................................................................. 25
GTL+ Asynchronous and AGTL+ Asynchronous Signals ................................... 27
Test Access Port (TAP) Connection.................................................................... 27
Maximum Ratings................................................................................................ 27
Processor DC Specifications............................................................................... 28
2.10.1 Flexible Motherboard (FMB) Guidelines................................................. 28
2.10.2 VCC and VCACHE Overshoot Specification.......................................... 32
2.10.3 Die Voltage Validation ............................................................................ 33
AGTL+ Front Side Bus Specifications .................................................................37
Front Side Bus AC Specifications ....................................................................... 37
Processor AC Timing Waveforms ....................................................................... 42
Front Side Bus Signal Quality Specifications and Measurement Guidelines ...... 53
3.1.1 Ringback Guidelines .............................................................................. 53
3.1.2 Overshoot/Undershoot Guidelines ......................................................... 56
3.1.3 Overshoot/Undershoot Magnitude ......................................................... 56
3.1.4 Overshoot/Undershoot Pulse Duration................................................... 57
3.1.5 Activity Factor......................................................................................... 57
3.1.6 Reading Overshoot/Undershoot Specification Tables............................ 57
3.1.7 Determining if a System Meets Over/Undershoot Specifications........... 58
Package Mechanical Drawing ............................................................................. 62
Processor Component Keep-Out Zones ............................................................. 65
Package Loading Specifications ......................................................................... 65
Package Handling Guidelines ............................................................................. 66
Package Insertion Specifications ........................................................................ 66
Processor Mass Specifications ........................................................................... 66
Processor Materials............................................................................................. 66
Processor Markings............................................................................................. 67
Processor Pin-Out Coordinates........................................................................... 68
Electrical Specifications.................................................................................................... 17
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3
3.1
Front Side Bus Signal Quality Specifications ................................................................... 53
4
Mechanical Specifications ................................................................................................ 61
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
64-bit Intel
®
Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
3
5
Pin Listing......................................................................................................................... 69
5.1
Processor Pin Assignments ................................................................................ 69
5.1.1 Pin Listing by Pin Name ......................................................................... 69
5.1.2 Pin Listing by Pin Number ...................................................................... 78
Signal Definitions ................................................................................................ 87
Package Thermal Specifications ......................................................................... 97
7.1.1 Thermal Specifications ........................................................................... 97
7.1.2 Thermal Metrology ............................................................................... 100
Processor Thermal Features............................................................................. 100
7.2.1 Thermal Monitor ................................................................................... 100
7.2.2 Thermal Monitor 2 ................................................................................ 101
7.2.3 On-Demand Mode................................................................................ 102
7.2.4 PROCHOT# Signal Pin ........................................................................ 103
7.2.5 FORCEPR# Signal Pin ........................................................................ 103
7.2.6 THERMTRIP# Signal Pin ..................................................................... 103
7.2.7 TCONTROL and Fan Speed Reduction............................................... 103
7.2.8 Thermal Diode...................................................................................... 104
Power-On Configuration Options ...................................................................... 105
Clock Control and Low Power States................................................................ 105
8.2.1 Normal State ........................................................................................ 106
8.2.2 HALT or Enhanced Power Down State ................................................ 106
8.2.3 Stop-Grant State .................................................................................. 107
8.2.4 Enhanced HALT Snoop State or HALT Snoop State,
Stop Grant Snoop State ....................................................................... 108
Enhanced Intel SpeedStep
®
Technology.......................................................... 108
System Management Bus (SMBus) Interface ................................................... 109
8.4.1 Processor Information ROM (PIROM).................................................. 110
8.4.2 Scratch EEPROM ................................................................................ 112
8.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions ......... 113
8.4.4 SMBus Thermal Sensor ....................................................................... 113
8.4.5 Thermal Sensor Supported SMBus Transactions ................................ 114
8.4.6 SMBus Thermal Sensor Registers ....................................................... 115
8.4.7 SMBus Thermal Sensor Alert Interrupt ................................................ 118
8.4.8 SMBus Device Addressing................................................................... 118
8.4.9 Managing Data in the PIROM .............................................................. 120
Introduction ....................................................................................................... 127
Mechanical Specifications ................................................................................. 128
9.2.1 Boxed Processor Heatsink Dimensions ............................................... 128
9.2.2 Boxed Processor Heatsink Weight....................................................... 135
9.2.3 Boxed Processor Retention Mechanism and Heatsink Supports......... 135
Thermal Specifications...................................................................................... 135
9.3.1 Boxed Processor Cooling Requirements ............................................. 135
9.3.2 Boxed Processor Contents .................................................................. 136
6
7
Signal Definitions ............................................................................................................. 87
6.1
7.1
Thermal Specifications..................................................................................................... 97
7.2
8
Features ......................................................................................................................... 105
8.1
8.2
8.3
8.4
9
Boxed Processor Specifications..................................................................................... 127
9.1
9.2
9.3
4
64-bit Intel
®
Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
10
Debug Tools Specifications............................................................................................137
10.1
Logic Analyzer Interface (LAI) ...........................................................................137
10.1.1 Mechanical Considerations ..................................................................137
10.1.2 Electrical Considerations......................................................................137
Figures
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
7-1
7-2
7-3
8-1
8-2
9-1
9-2
9-3
9-4
On-Die Front Side Bus Termination .................................................................... 17
Phase Lock Loop (PLL) Filter Requirements ...................................................... 20
Processor Load Current vs. Time........................................................................ 30
VCC Static and Transient Tolerance................................................................... 32
VCC and VCACHE Overshoot Example Waveform............................................ 33
Electrical Test Circuit........................................................................................... 42
TCK Clock Waveform.......................................................................................... 43
Differential Clock Waveform................................................................................ 43
Differential Clock Crosspoint Specification.......................................................... 44
Front Side Bus Common Clock Valid Delay Timing Waveform........................... 44
Source Synchronous 2X (Address) Timing Waveform........................................ 45
Source Synchronous 4X (Data) Timing Waveform ............................................. 46
TAP Valid Delay Timing Waveform ..................................................................... 47
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform ... 47
THERMTRIP# Power Down Sequence............................................................... 47
SMBus Timing Waveform.................................................................................... 48
SMBus Valid Delay Timing Waveform ................................................................ 48
Voltage Sequence Timing Requirements............................................................ 49
VIDPWRGD Timing Requirements ..................................................................... 50
FERR#/PBE# Valid Delay Timing ....................................................................... 50
VID Step Timings ................................................................................................ 51
VID Step Times and VCC Waveforms ................................................................ 51
Low-to-High Front Side Bus Receiver Ringback Tolerance ................................ 54
High-to-Low Front Side Bus Receiver Ringback Tolerance ................................ 54
Low-to-High Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 55
High-to-Low Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 56
Maximum Acceptable Overshoot/Undershoot Waveform ................................... 60
Processor Package Assembly Sketch.................................................................61
Processor Package Drawing (Sheet 1 of 2) ........................................................ 63
Processor Package Drawing (Sheet 2 of 2) ........................................................ 64
Processor Topside Markings............................................................................... 67
Processor Bottom-Side Markings........................................................................ 67
Processor Pin-Out Coordinates, Top View.......................................................... 68
64-bit Intel
®
Xeon™ Processor MP with up to 8MB L3 Cache Thermal Profile .. 99
Case Temperature (TCASE) Measurement Location .......................................100
Thermal Monitor 2 Frequency and Voltage Ordering ........................................102
Stop Clock State Machine .................................................................................107
Logical Schematic of SMBus Circuitry ..............................................................110
Passive Processor Thermal Solution (3U and larger) .......................................128
Top Side Board Keep-Out Zones (Part 1) .........................................................129
Top Side Board Keep-Out Zones (Part 2) .........................................................130
Bottom Side Board Keep-Out Zones.................................................................131
64-bit Intel
®
Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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