64-bit Intel
®
Xeon™ Processor
MP with 1MB L2 Cache
Datasheet
March 2005
Document Number:
306751-001
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ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 64-bit Intel
®
Xeon™ processor MP with 1MB L2 cache may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Intel, Pentium, Intel Xeon, Intel NetBurst, Intel SpeedStep, Intel Extended Memory 64 Technology and the Intel logo are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
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64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Datasheet
Contents
1
Introduction....................................................................................................................... 11
1.1
Terminology......................................................................................................... 12
1.2
Reference Documents......................................................................................... 14
1.3
State of Data ....................................................................................................... 14
Electrical Specifications....................................................................................................15
2.1
Front Side Bus Clock and Processor Clocking.................................................... 15
2.1.1 Front Side Bus Clock Select (BSEL[1:0]) ............................................... 16
2.1.2 Phase Lock Loop (PLL) Power and Filter............................................... 16
2.2
Voltage Identification (VID)..................................................................................17
2.3
Reserved, Unused, and TESTHI Pins................................................................. 19
2.4
Mixing Processors ............................................................................................... 20
2.5
Front Side Bus Signal Groups............................................................................. 20
2.6
GTL+ Asynchronous Signals and AGTL + Asynchronous Signals...................... 22
2.7
Test Access Port (TAP) Connection....................................................................22
2.8
Absolute Maximum and Minimum Ratings .......................................................... 22
2.9
Processor DC Specifications............................................................................... 23
2.9.1 Flexible Motherboard (FMB) Guidelines................................................. 23
2.9.2 Vcc Overshoot Specification .................................................................. 27
2.10
AGTL+ Front Side Bus Specifications ................................................................. 31
2.11
Front Side Bus AC Specifications .......................................................................32
2.12
Processor AC Timing Waveforms ....................................................................... 36
Front Side Bus Signal Quality Specifications ...................................................................45
3.1
Front Side Bus Signal Quality Specifications and Measurement Guidelines ...... 45
3.1.1 Ringback Guidelines .............................................................................. 45
3.1.2 Overshoot/Undershoot Guidelines ......................................................... 48
3.1.3 Overshoot/Undershoot Magnitude .........................................................48
3.1.4 Overshoot/Undershoot Pulse Duration................................................... 48
3.1.5 Activity Factor......................................................................................... 48
3.1.6 Reading Overshoot/Undershoot Specification Tables............................ 49
3.1.7 Determining if a System Meets the Overshoot/Undershoot
Specifications ......................................................................................... 50
Mechanical Specifications ................................................................................................ 53
4.1
Package Mechanical Drawing ............................................................................. 53
4.2
Processor Component Keepout Zones ............................................................... 56
4.3
Package Loading Specifications ......................................................................... 56
4.4
Package Handling Guidelines ............................................................................. 57
4.5
Package Insertion Specifications ........................................................................ 57
4.6
Processor Mass Specifications ...........................................................................57
4.7
Processor Materials............................................................................................. 57
4.8
Processor Markings............................................................................................. 58
4.9
Processor Pin-Out Coordinates........................................................................... 59
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3
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64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Datasheet
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5
Pin Listing......................................................................................................................... 61
5.1
64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Pin Assignments......... 61
5.1.1 Pin Listing by Pin Name ......................................................................... 61
5.1.2 Pin Listing by Pin Number ...................................................................... 70
Signal Definitions ............................................................................................................. 79
6.1
Signal Definitions ................................................................................................ 79
Thermal Specifications..................................................................................................... 87
7.1
Package Thermal Specifications ......................................................................... 87
7.1.1 Thermal Specifications ........................................................................... 87
7.1.2 Thermal Metrology ................................................................................. 89
7.2
Processor Thermal Features............................................................................... 90
7.2.1 Thermal Monitor ..................................................................................... 90
7.2.2 Thermal Monitor 2 .................................................................................. 91
7.2.3 On-Demand Mode.................................................................................. 92
7.2.4 PROCHOT# Signal Pin .......................................................................... 93
7.2.5 FORCEPR# Signal Pin .......................................................................... 93
7.2.6 THERMTRIP# Signal Pin ....................................................................... 93
7.2.7 Tcontrol and Fan Speed Reduction ....................................................... 94
7.2.8 Thermal Diode........................................................................................ 94
Features ........................................................................................................................... 95
8.1
Power-On Configuration Options ........................................................................ 95
8.2
Clock Control and Low Power States.................................................................. 95
8.2.1 Normal State—State 1 ........................................................................... 95
8.2.2 HALT Power Down State—State 2 ........................................................ 95
8.2.3 Stop-Grant State—State 3 ..................................................................... 96
8.2.4 HALT/Grant Snoop State—State 4 ........................................................ 97
8.3
Enhanced Intel SpeedStep Technology .............................................................. 97
8.4
System Management Bus (SMBus) Interface ..................................................... 98
8.4.1 Processor Information ROM (PIROM).................................................... 99
8.4.2 Scratch EEPROM ................................................................................ 101
8.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions ......... 101
8.4.4 SMBus Thermal Sensor ....................................................................... 101
8.4.5 Thermal Sensor Supported SMBus Transactions ................................ 102
8.4.6 SMBus Thermal Sensor Registers ....................................................... 104
8.4.7 SMBus Thermal Sensor Alert Interrupt ................................................ 106
8.4.8 SMBus Device Addressing................................................................... 106
8.4.9 Managing Data in the PIROM .............................................................. 108
Boxed Processor Specifications..................................................................................... 113
9.1
Introduction ....................................................................................................... 113
9.2
Mechanical Specifications ................................................................................. 114
9.2.1 Boxed Processor Heatsink Dimensions ............................................... 114
9.2.2 Boxed Processor Heatsink Weight....................................................... 121
9.2.3 Boxed Processor Retention Mechanism and Heatsink Supports......... 121
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7
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64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Datasheet
9.3
Thermal Specifications ......................................................................................121
9.3.1 Boxed Processor Cooling Requirements ............................................. 121
9.3.2 Boxed Processor Contents................................................................... 122
10
Debug Tools Specifications............................................................................................123
10.1
Logic Analyzer Interface (LAI) ...........................................................................123
10.1.1 Mechanical Considerations ..................................................................123
10.1.2 Electrical Considerations......................................................................123
Figures
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
7-1
7-2
Phase Lock Loop (PLL) Filter Requirements ......................................................17
64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Load
Current vs. Time.................................................................................................. 25
VCC Static and Transient Tolerance ...................................................................26
V
CC
Overshoot Example Waveform.................................................................... 27
Electrical Test Circuit........................................................................................... 36
TCK Clock Waveform.......................................................................................... 36
Differential Clock Waveform................................................................................ 37
Differential Clock Crosspoint Specification.......................................................... 37
Front Side Bus Common Clock Valid Delay Timing Waveform........................... 38
Source Synchronous 2X (Address) Timing Waveform........................................ 38
Source Synchronous 4X (Data) Timing Waveform ............................................. 39
TAP Valid Delay Timing Waveform ..................................................................... 39
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform ...40
THERMTRIP# Power Down Sequence............................................................... 40
SMBus Timing Waveform.................................................................................... 40
SMBus Valid Delay Timing Waveform ................................................................ 41
Voltage Sequence Timing Requirements ............................................................ 41
VIDPWRGD Timing Requirements ..................................................................... 42
FERR#/PBE# Valid Delay Timing ....................................................................... 42
VID Signal Group AC Specifications ................................................................... 43
VID Transition Times...........................................................................................43
Low-to-High Front Side Bus Receiver Ringback Tolerance ................................ 46
High-to-Low Front Side Bus Receiver Ringback Tolerance ................................ 46
Low-to-High Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 47
High-to-Low Receiver Ringback Tolerance for PWRGOOD and TAP Signals ...47
Maximum Acceptable Overshoot/Undershoot Waveform ................................... 52
Processor Package Assembly Sketch.................................................................53
Processor Package Drawing (Sheet 1 of 2) ........................................................ 54
Processor Package Drawing (Sheet 2 of 2) ........................................................ 55
Processor Topside Markings ...............................................................................58
Processor Bottom-Side Markings........................................................................ 58
Processor Pin-Out Coordinates, Top View.......................................................... 59
64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Thermal Profile A ........88
Case Temperature (TCASE) Measurement Location ......................................... 90
64-bit Intel
®
Xeon™ Processor MP with 1MB L2 Cache Datasheet
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