EP1S20F780I7 datasheet, PDF - EEWORLD Datasheet

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EP1S20F780I7: DescriptionField Programmable Gate Array, 18460-Cell, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780; CategoryProgrammable logic devices Programmable logic; File Size3MB，276 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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EP1S20F780I7 Overview

Field Programmable Gate Array, 18460-Cell, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780

EP1S20F780I7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
package instruction	29 X 29 MM, 1 MM PITCH, FBGA-780
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B780
JESD-609 code	e0
Number of entries	586
Number of logical units	18460
Output times	586
Number of terminals	780
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA780,28X28,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

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Section I. Stratix Device

Family Data Sheet

This section provides the data sheet specifications for Stratix

devices.

They contain feature definitions of the internal architecture,

configuration and JTAG boundary-scan testing information, DC

operating conditions, AC timing parameters, a reference to power

consumption, and ordering information for Stratix devices.

This section contains the following chapters:

■

Chapter 1, Introduction

Chapter 2, Stratix Architecture

Chapter 3, Configuration & Testing

Chapter 4, DC & Switching Characteristics

Chapter 5, Reference & Ordering Information

Revision History

Chapter

The table below shows the revision history for

Chapters 1

through

Date/Version

July 2005, v3.2

September 2004, v3.1

April 2004, v3.0

●

Changes Made

Minor content changes.

Updated

Table 1–6 on page 1–5.

Main section page numbers changed on first page.

Changed PCI-X to PCI-X 1.0 in

“Features” on page 1–2.

Global change from SignalTap to SignalTap II.

The DSP blocks in

“Features” on page 1–2

provide dedicated

implementation of multipliers that are now “faster than 300 MHz.”

Updated -5 speed grade device information in Table 1-6.

Add -8 speed grade device information.

Format changes throughout chapter.

January 2004, v2.2

October 2003, v2.1

July 2003, v2.0

●

Altera Corporation

Section I–1

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