The 82375EB SB PCI-EISA Bridge (PCEB) provides the master slave functions on both the PCI Local Bus
and the EISA Bus Functioning as a bridge between the PCI and EISA buses the PCEB provides the address
and data paths bus controls and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers Exten-
sive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficien-
cy and allowing concurrency on the two buses The PCEB’s buffer management mechanism ensures data
coherency The PCEB integrates central bus control functions including a programmable bus arbiter for the
PCI Bus and EISA data swap buffers for the EISA Bus Integrated system functions include PCI parity genera-
tion system error reporting and programmable PCI and EISA memory and I O address space mapping and
decoding The PCEB also contains a BIOS Timer that can be used to implement timing loops The PCEB is
intended to be used with the EISA System Component (ESC) to provide an EISA I O subsystem interface
This document describes both the 82375EB and 82375SB components Unshaded areas describe the
82375EB Shaded areas like this one describe the 82375SB operations that differ from the 82375EB
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1996
March 1996
Order Number 290477-004
82375EB SB
290477 –1
PCEB Simplified Block Diagram
2
82375EB 82375SB PCI-EISA BRIDGE (PCEB)
CONTENTS
1 0 ARCHITECTURAL OVERVIEW
1 1 PCEB Overview
1 2 ESC Overview
2 0 SIGNAL DESCRIPTION
2 1 PCI Bus Interface Signals
2 2 PCI Arbiter Signals
2 3 Address Decoder Signals
2 4 EISA Interface Signals
2 5 ISA Interface Signals
2 6 PCEB ESC Interface Signals
2 7 Test Signal
3 0 REGISTER DESCRIPTION
3 1 Configuration Registers
3 1 1 VID VENDOR IDENTIFICATION REGISTER
3 1 2 DID DEVICE IDENTIFICATION REGISTER
3 1 3 PCICMD PCI COMMAND REGISTER
3 1 4 PCISTS PCI STATUS REGISTER
3 1 5 RID REVISION IDENTIFICATION REGISTER
3 1 6 MLT MASTER LATENCY TIMER REGISTER
3 1 7 PCICON PCI CONTROL REGISTER
3 1 8 ARBCON PCI ARBITER CONTROL REGISTER
3 1 9 ARBPRI PCI ARBITER PRIORITY CONTROL REGISTER
3 1 10 ARBPRIX PCI ARBITER PRIORITY CONTROL EXTENSION REGISTER
3 1 11 MCSCON MEMCS CONTROL REGISTER
3 1 12 MCSBOH MEMCS BOTTOM OF HOLE REGISTER
3 1 13 MCSTOH MEMCS TOP OF HOLE REGISTER
3 1 14 MCSTOM MEMCS TOP OF MEMORY REGISTER
3 1 15 EADC1 EISA ADDRESS DECODE CONTROL 1 REGISTER
3 1 16 IORT ISA I O RECOVERY TIMER REGISTER
3 1 17 MAR1 MEMCS ATTRIBUTE REGISTER 1
3 1 18 MAR2 MEMCS ATTRIBUTE REGISTER 2
3 1 19 MAR3 MEMCS ATTRIBUTE REGISTER 3
3 1 20 PDCON PCI DECODE CONTROL REGISTER
3 1 21 EADC2 EISA ADDRESS DECODE CONTROL EXTENSION REGISTER
PAGE
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3
CONTENTS
3 1 22 EPMRA EISA-TO-PCI MEMORY REGION ATTRIBUTES REGISTER
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