Operated at Commercial and Industrial Temperature Ranges.
PRELIMINARY
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.1
History
Initial release with Preliminary.
Change Icc. Isb and Isb1
Item
I
CC(Commercial)
10ns
12ns
15ns
10ns
12ns
15ns
Previous
90mA
80mA
70mA
115mA
100mA
85mA
30mA
10mA
Current
65mA
55mA
45mA
85mA
75mA
65mA
20mA
5mA
Draft Data
September. 7. 2001
November, 3. 2001
Remark
Preliminary
Preliminary
I
CC(Industrial)
I
SB
I
SB1
Rev. 0.2
1. Correct AC parameters : Read & Write Cycle mA
2. Delete Low Ver.
3. Delete Data Retention Characteristics
1. Delete 15ns speed bin.
2. Change Icc for Industrial mode.
Item
10ns
I
CC(Industrial)
12ns
November, 3. 2001
Preliminary
Rev. 0.3
Previous
85mA
75mA
Current
75mA
65mA
December, 18. 2001
Preliminary
Rev. 1.0
1. Final datasheet release.
2. Delete 12ns speed bin.
3. Delete UB,LB releated AC characteristics and timing diagram.
4. Correct Read Cycle time waveform(2).
1. Add the Lead Free Package type.
July, 09, 2002
Final
Rev. 2.0
July. 26, 2004
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev. 2.0
July 2004
K6R4004C1D
4Mb Async. Fast SRAM Ordering Information
Org.
1M x4
K6R4004V1D-J(K)C(I) 08/10
K6R4008C1D-J(K,T,U)C(I) 10
512K x8
K6R4008V1D-J(K,T,U)C(I) 08/10
K6R4016C1D-J(K,T,U,E)C(I) 10
256K x16
K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10
3.3
5
3.3
8/10
10
8/10
3.3
5
8/10
10
Part Number
K6R4004C1D-J(K)C(I) 10
VDD(V)
5
Speed ( ns )
10
PKG
J : 32-SOJ
K : 32-SOJ(LF)
PRELIMINARY
CMOS SRAM
Temp. & Power
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
J : 36-SOJ
K : 36-SOJ(LF)
,Normal Power Range
T : 44-TSOP2
L : Commercial Temperature
U : 44-TSOP2(LF)
,Low Power Range
P : Industrial Temperature
J : 44-SOJ
,Low Power Range
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
-2-
Rev. 2.0
July 2004
K6R4004C1D
1M x 4 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4004C1D-10 : 65mA(Max.)
Single 5.0V±10
%
Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4004C1D-J : 32-SOJ-400
K6R4004C1D-K : 32-SOJ-400(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
PRELIMINARY
CMOS SRAM
GENERAL DESCRIPTION
The K6R4004C1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1D uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4004C1D is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
A
0
A
1
A
2
A
3
A
4
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
A
19
A
18
A
17
A
16
A
15
OE
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
1
~I/O
4
I/O
1
Vcc
Vss
26 I/O
4
SOJ
25
24
Vss
Vcc
Pre-Charge Circuit
I/O
2
WE
A
5
23 I/O
3
22
21
20
19
18
A
14
A
13
A
12
A
11
A
10
Row Select
A
6
Memory Array
1024 Rows
1024 x 4 Columns
A
7
A
8
A
9
17 N.C
Data
Cont.
CLK
Gen.
A
10
I/O Circuit
Column Select
PIN FUNCTION
Pin Name
A
0
- A
19
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
A
12
A
14
A
16
A
18
A
11
A
13
A
15
A
17
A
19
CS
WE
OE
-3-
Rev. 2.0
July 2004
K6R4004C1D
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to V
CC+
0.5
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
PRELIMINARY
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5*
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5**
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
**
V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
***
V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Com.
Ind.
10ns
10ns
Test Conditions
Min
-2
-2
-
-
-
-
-
2.4
Max
2
2
65
75
20
5
0.4
-
V
V
Unit
µA
µA
I
CC
I
SB
mA
mA
Standby Current
Output Low Voltage Level
Output High Voltage Level
I
SB1
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
TYP
-
-
Max
8
6
Unit
pF
pF
-4-
Rev. 2.0
July 2004
K6R4004C1D
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
PRELIMINARY
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
R
L
= 50Ω
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
480Ω
D
OUT
255Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
K6R4004C1D-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
京公网安备 11010802033920号
EEWORLD
