October 2003
rev 1.0
Peak Reducing EMI Solution
Features
•
•
•
•
•
•
•
FCC approved method of EMI
attenuation.
Provides up to 15dB EMI reduction.
Generates a low EMI spread spectrum
clock and a non-spread reference clock
of the input frequency.
Optimized for frequency range from
20MHz to 40MHz.
Internal loop filter minimizes external
components and board space.
Selectable spread options: Down and
Center Spread.
Low inherent cycle-to-cycle jitter.
ASM3P1819A-H
•
•
•
•
•
•
•
•
Eight Spread % Selections:
o
± 0.625% to –3.5%.
3.3V operating voltage.
CMOS/TTL compatible inputs and
outputs.
Low-power CMOS design.
Supports notebook VGA and other LCD
timing controller applications.
Power down function for mobile
application.
Products are available for industrial
temperature range.
Available in 8-pin SOIC and TSSOP
packages.
Product Description
The ASM3P1819x is a versatile spread
spectrum
frequency
modulator
designed
specifically for input clock frequencies from
20MHz to 40MHz. The ASM3P1819x can
generate an EMI reduced clock form an OSC or
a system-generated clock. The ASM3P1819x
offers Down and Center spread options with
different percentage deviations.
(Refer Spread
Deviation Selections Table.)
The ASM3P1819x reduces electromagnetic
interference (EMI) at the clock source, allowing
system wide reduction of EMI of down stream
clock and data dependent signals. The
ASM3P1819x allows significant system cost
savings by reducing the number of circuit board
layers and shielding that are traditionally
required to pass EMI regulations.
The ASM3P1819x modulates the output of a
single PLL in order to “spread” the bandwidth of
a synthesized clock, thereby decreasing the
peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by
oscillators and most clock generators. Lowering
EMI by increasing a signal’s bandwidth is called
spread spectrum clock generation.
The ASM3P1819x uses the most efficient and
optimized modulation profile approved by the
FCC and is implemented by using a proprietary
all-digital method.
Applications
The ASM3P1819x is targeted towards EMI
management for memory and LVDS interfaces
in mobile graphic chipsets and high-speed digital
applications such as PC peripheral devices,
consumer electronics, and embedded controller
systems.
Alliance Semiconductor
2595, Augustine Drive
•
Santa Clara
•
CA 95054
•
Tel 408 855 4900
•
Fax 408 855 4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
Octoberr 2003
rev 1.0
Block Diagram
D_C
PD# SRS
VDD
ASM3P1819A-H
Modulation
XIN
Crystal
Oscillator
XOUT
Feedback
Divider
Frequency
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
REF
VSS
Pin Diagram
XIN
VSS
SRS
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
XIN
VSS
D_C
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
ASM3P1819A-D
ASM3P1819E-H
Pin Description
Pin Name
ASM3P1819A-D
ASM3P1819E-H
Pin#
1
2
3
XIN
VSS
D_C
Type
XIN
VSS
I
P
I
Description
Connect to externally generated clock signal or crystal.
Ground to entire chip.
Digital logic input used to select Down (LOW) or Center
(HIGH) spread options (Refer
Spread Deviation
Selection Table.)
This pin has an internal pull-up
resistor.
Spread range select. Digital logic input used to select
frequency deviation (Refer
Spread Deviation Selection
Table.)
Spread spectrum clock output.
Un-modulated reference output clock of the input
frequency.
Power-Down control pin. Pull LOW to enable Power-
Down mode. This pin has an internal pull-up resistor.
Connect to +3.3V.
Crystal connection. If connected to an externally
generated clock, this pin must be left unconnected.
3
4
5
6
7
8
ModOUT
REF
PD#
VDD
XOUT
SRS
ModOUT
REF
PD#
REF
XOUT
I
O
O
I
P
O
Low EMI Clock for Mobile VGA
Notice: The information in this document is subject to change without notice.
2 of 8
Octoberr 2003
rev 1.0
DC Electrical Characteristics
Unless otherwise noted, V
DD
= 3.3V and T
A
=25°C
ASM3P1819A-H
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Parameter
Min
GND – 0.3
2.00
-60.0
-
2.00
-
-
2.8
7.1 f
IN
- min
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
4.5
3.3
0.18
50
Max
0.8
V
DD
+ 0.3
-20.0
1.00
12.00
12.00
0.4
-
26.9 f
IN
- max
-
-
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
Input low current (inputs D_C, PD#)
Input high current
X
OUT
output low current (@ 0.4V, V
DD
= 3.3V)
X
OUT
output high current (@2.5V, V
DD
= 3.3V)
Output low voltage (V
DD
= 3.3V, I
OL
= 20mA)
Output high voltage (V
DD
= 3.3V, I
OH
= 20mA)
Dynamic supply current normal mode (3.3V and
10pF loading)
Static supply current standby mode
Operating voltage
Power up time (first locked clock cycle after power
up)
Clock output impedance
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
*
t
HL
*
t
JC
Parameter
Input frequency
Output frequency
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Min
20
20
-
-
-200
45
Typ
-
-
0.69
0.66
-
50
Max
40
40
-
-
200
55
Unit
MHz
MHz
ns
ns
ps
%
t
D
Output duty cycle
* t
LH
and t
HL
are measured into a capacitive load of 15pF
Low EMI Clock for Mobile VGA
Notice: The information in this document is subject to change without notice.
4 of 8
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
