A0900APY3A datasheet, PDF - EEWORLD Datasheet

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A0900APY3A: DescriptionMicroprocessor, 32-Bit, 900MHz, CMOS, CPGA462, STAGGERED, PGA-453; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，84 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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A0900APY3A Overview

Microprocessor, 32-Bit, 900MHz, CMOS, CPGA462, STAGGERED, PGA-453

A0900APY3A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	PGA
package instruction	IPGA, SPGA462,37X37
Contacts	453
Reach Compliance Code	unknown
ECCN code	3A001.A.3
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P462
JESD-609 code	e0
length	49.53 mm
low power mode	YES
Number of terminals	462
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Encapsulate equivalent code	SPGA462,37X37
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.7,2.5 V
Certification status	Not Qualified
Maximum seat height	3.422 mm
speed	900 MHz
Maximum supply voltage	1.85 V
Minimum supply voltage	1.65 V
Nominal supply voltage	1.7 V
surface mount	NO
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Preliminary Information

AMD Athlon

Processor

PGA

Data Sheet

Publication #

23792

Rev:

Issue Date:

August 2000

Preliminary Information

23792C—August 2000

AMD Athlon™ Processor PGA Data Sheet

Contents

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

About This Data Sheet1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1

2.1

2.2

2.3

2.4

AMD Athlon™ Processor Microarchitecture Summary . . . . . 4

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

AMD Athlon System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 8

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 13

Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 23

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 23

SYSCLK and SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 24

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 26

AMD Athlon System Bus Pins AC/DC Characteristics . . . . . 27

AMD Athlon System Bus AC Characteristics . . . . . . . . . . . . 28

General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 29

APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 31

Contents

iii

Preliminary Information

AMD Athlon™ Processor PGA Data Sheet

23792C—August 2000

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 33

7.1

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 33

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 36

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 38

The AMD Athlon Processor and Northbridge Reset Pins . . . 38

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . 59

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . . . . 59

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 59

DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 61

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SADDIN[1]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . . 62

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SCHECK[7:0]# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

SYSCLK and SYSCLK# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 63

SYSVREFMODE Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

ZN, VCC_Z, ZP, and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . . . . 64

7.2

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1

8.2

8.3

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1

9.2

9.3

Contents

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