LSI/CSI
UL
®
LS7083
LS7084
(631) 271-0400 FAX (631) 271-0405
September 2006
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
QUADRATURE CLOCK CONVERTER
FEATURES:
• x1 and x4 mode selection
• Up to 16MHz output clock frequency
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +4.5V to +10V operation (V
DD
- V
SS
)
• LS7083, LS7084 (DIP);
LS7083-S, LS7084-S (SOIC) -
See Figure 1
DESCRIPTION:
The LS7083 and LS7084 are CMOS quadrature clock con-
verters. Quadrature clocks derived from optical or magnetic
encoders, when applied to the A and B inputs of the LS7083/
LS7084, are converted to strings of Up Clocks and Down
Clocks (LS7083) or to a Clock and an Up/Down direction
control (LS7084). These outputs can be interfaced directly
with standard Up/Down counters for direction and position
sensing of the encoder.
INPUT/OUTPUT DESCRIPTION:
RBIAS
(Pin 1)
Input for external component connection. A resistor con-
nected between this input and V
SS
adjusts the output clock
pulse width (Tow). For proper operation, the output clock
pulse width must be less than or equal to the A, B pulse
separation (T
OW
≤
T
PS)
.
V
DD
(Pin 2)
Supply Voltage positive terminal.
V
SS
(Pin 3
)
Supply Voltage negative terminal.
A
(Pin 4)
Quadrature Clock Input A. This input has a filter circuit to
validate input logic level and eliminate encoder dither.
B
(Pin 5)
Quadrature Clock Input B. This input has a filter circuit
identical to input A.
x4/x1
(Pin 6)
This input selects between x1 and x4 modes of operation.
A high-level selects x4 mode and a low-level selects the x1
mode. In x4 mode, an output pulse is generated for every
transition at either A or B input. In x1 mode, an output
pulse is generated in one combined A/B input cycle.
(See Figure 2.)
7083/84-092806-1
PIN ASSIGNMENT - TOP VIEW
RBIAS
))
V
DD
(+V
1
8
7
6
UPCK
LSI
LS7083
2
3
4
DNCK
x4/x1
V
SS
(-V)
A
5
B
LSI
RBIAS
V
DD
(+V )
1
2
8
7
CLK
UP/DN
x4/x1
LS7084
V
SS
(-V )
A
3
6
5
4
B
FIGURE 1
LS7083 - DNCK
(Pin 7)
In LS7083, this is the DOWN Clock Output. This output con-
sists of low-going pulses generated when A input lags the B
input.
LS7084 - UP/DN
(Pin 7)
In LS7084, this is the count direction indication output.
When A input leads the B input, the UP/DN output goes high
indicating that the count direction is UP. When A input lags
the B input, UP/DN output goes low, indicating that the count
direction is DOWN.
LS7083 - UPCK
(Pin 8)
In LS7083, this is the UP Clock output. This output consists
of low-going pulses generated when A input leads the B in-
put.
LS7084 - CLK
(Pin 8)
In LS7084, this is the combined UP Clock and DOWN Clock
output. The count direction at any instant is indicated by the
UP/DN output (Pin 7).
NOTE:
For the LS7084, the timing of CLK and UP/DN re-
quires that the counter interfacing with LS7084 counts on the
rising edge of the CLK pulses.
1500
V
DD
=5V
30
V
DD
=5V
25
OUTPUT CLOCK PULSE WIDTH, Tow, ns
V
DD
=9V
V
DD
=10.0V
OUTPUT CLOCK PULSE WIDTH, Tow, µs
1250
1000
20
V
DD
=9V
750
15
V
DD
=10.0V
500
10
250
5
100
200
300
400
500
2
4
6
8
10
12
Figure 4. Tow vs RBIAS, K
Figure 5. Tow vs RBIAS, M
+V
6
x4/x1
A CLOCK
ENCODER
B CLOCK
4
5
A
B
LS7083
DNCK
V
SS
3
2
V
DD
UPCK
8
5
+V
16
V
DD
CK-UP
40193
CK-DN
7
4
1
R
B
RBIAS
V
SS
8
FIGURE 6A. TYPICAL APPLICATION FOR LS7083 IN x4 MODE
MODE SELECT
R
6
x4/x1
A CLOCK
ENCODER
B CLOCK
4
5
A
B
RBIAS
V
SS
R
B
3
+V
2
V
DD
CLK
LS7084
UP/DN
8
7
15
CK
10
4516
UP/DN
V
SS
8
+V
16
V
DD
1
FIGURE 6B. TYPICAL APPLICATION FOR LS7084 WITH x4/x1 MODE SELECTION
Note:
The CLK Output of LS7184 can be applied directly to the Clock Input of counters that advance on the positive edge
of the Clock Input. If the Counter advances on the negative edge of the Clock Input, an inverter must be added between
the CLK Output of LS7184 and the Clock Input of the Counter.
7083/84-092806-4
RF/Wirelessly
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