BSL316C
OptiMOS™ 2 + OptiMOS™-P 2 Small Signal Transistor
Product Summary
Features
P
·
Complementary P + N channel
·
Enhancement mode
·
Logic level (4.5V rated)
·
Avalanche rated
I
D
·
Qualified according to AEC Q101
·
100% lead-free; RoHS compliant
·
Halogen free according to IEC61249-2-21
6
5
4
N
30
160
280
1.4
A
V
mW
V
DS
R
DS(on),max
V
GS
=±10 V
V
GS
=±4.5 V
-30
150
270
-1.5
PG-TSOP6
1
2
3
Type
BSL316C
Package
PG-TSOP-6
Tape and Reel Information
H6327: 3000 pcs / reel
Marking
sPJ
Lead Free
Yes
Packing
Non dry
Maximum ratings,
at
T
j
=25 °C, unless otherwise specified
1)
Parameter
Symbol Conditions
P
Continuous drain current
I
D
T
A
=25 °C
T
A
=70 °C
Pulsed drain current
I
D,pulse
E
AS
V
GS
P
tot
T
j
,
T
stg
JESD22-A114-HBM
T
solder
T
A
=25 °C
T
A
=25 °C
P:
I
D
=-1.5 A,
N:
I
D
=1.4 A,
R
GS
=25
W
-1.5
-1.2
-6.0
Value
N
1.4
1.1
5.6
A
Unit
Avalanche energy, single pulse
11
3.7
mJ
Gate source voltage
Power dissipation
1)
Operating and storage temperature
ESD class
Soldering temperature
IEC climatic category; DIN IEC 68-1
1)
±20
0.5
-55 ... 150
0 (<250V)
260
55/150/56
V
W
°C
°C
Remark: only one of both transistors active
Rev. 2.3
page 1
2014-07-21
BSL316C
Parameter
Symbol Conditions
min.
Thermal characteristics
Thermal resistance, junction -
ambient
1)
P
N
minimal footprint
2)
Values
typ.
max.
Unit
R
thJA
-
-
250
K/W
Electrical characteristics,
at
T
j
=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
P
V
(BR)DSS
V
GS
=0 V,
I
D
=-250 µA
N
Gate threshold voltage
P
V
GS(th)
N
Zero gate voltage drain current
P
I
DSS
N
V
GS
=0 V,
I
D
=250 µA
V
DS
=V
GS
,
I
D
=-11 µA
V
DS
=V
GS
,
I
D
=3.7 µA
V
DS
=-30 V,
V
GS
=0 V,
T
j
=25 °C
V
DS
=30 V,
V
GS
=0 V,
T
j
=25 °C
V
DS
=-30 V,
V
GS
=0 V,
T
j
=150 °C
V
DS
=30 V,
V
GS
=0 V,
T
j
=150 °C
I
GSS
V
GS
=±20 V,
V
DS
=0 V
V
GS
=-4.5 V,
I
D
=-
1.1 A
V
GS
=4.5 V,
I
D
=-1.1 A
V
GS
=-10 V,
I
D
=-1.5 A
V
GS
=10 V,
I
D
=1.4 A
|V
DS
|>2|I
D
|R
DS(on)max
,
I
D
=-1.18 A
|V
DS
|>2|I
D
|R
DS(on)max
,
I
D
=1.1 A
-
30
-2
1.2
-
-
-
-
-1.5
1.6
-
-
-30
-
-1
2
-1
1
µA
V
P
N
Gate-source leakage current
P
N
Drain-source on-state
resistance
P
R
DS(on)
N
P
N
Transconductance
P
g
fs
-
-
-
-
-100
100
-
-
-
-
-
-
-
177
191
113
119
2.7
±100
270
280
150
160
-
nA
mW
S
N
2)
-
2.3
-
Performed on 40mm
2
FR4 PCB. The traces are 1mm wide, 70μm thick and 20mm long; they are present on both
sides of the PCB
Rev. 2.3
page 2
2014-07-21
FPGA/CPLD
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