MCP3914
3V Eight-Channel Analog Front End
Features:
• Eight Synchronous Sampling 24-Bit Resolution
Delta-Sigma Analog-to-Digital (A/D) Converters
• 94.5 dB SINAD, -107 dBc Total Harmonic
Distortion (THD) (up to 35
th
Harmonic), 112 dBFS
SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement
Error Over a 10,000:1 Dynamic Range
• Advanced Security Features:
- 16-Bit Cyclic Redundancy Check (CRC)
Checksum on All Communications for Secure
Data Transfers
- 16-Bit CRC checksum and Interrupt Alert for
Register Map Configuration
- Register Map Lock with 8-Bit Secure Key
• 2.7V-3.6V AV
DD
, DV
DD
• Programmable Data Rate Up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
- 16 MHz Maximum Master Clock
• Oversampling Ratio Up to 4096
• Ultra-Low Power Shutdown Mode with < 10 µA
• -122 dB Crosstalk Between Channels
• Low-Drift 1.2V Internal Voltage Reference: 9 ppm/°C
• Differential Voltage Reference Input Pins
• High-Gain Programmable Gain Amplifier (PGA)
on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Data Ready Pin for Easy Synchronization
• Individual 24-Bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz Serial Peripheral Interface
(SPI) with Mode 0,0 and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication Time with Dedicated
16/32-Bit Modes
• Available in a 40-Lead UQFN Package
• Extended Temperature Range: -40°C to +125°C
Description:
The MCP3914 is a 3V eight-channel Analog Front End
(AFE) containing eight synchronous sampling Delta-
Sigma Analog-to-Digital Converters (ADC), eight PGAs,
phase delay compensation block, low-drift internal volt-
age reference, Digital Offset and Gain Error Calibration
registers, and high-speed 20 MHz SPI compatible serial
interface.
The MCP3914 ADCs are fully configurable with features
such as: 16/24-bit resolution, Oversampling Ratio (OSR)
from 32 to 4096, gain from 1x to 32x, independent
shutdown and Reset, dithering and auto-zeroing. The
communication is largely simplified with 8-bit commands,
including various continuous Read/Write modes and
16/24/32-bit data formats that can be accessed by the
Direct Memory Access (DMA) of an 8, 16 or 32-bit MCU,
and with the separate Data Ready pin that can directly be
connected to an Interrupt Request (IRQ) input of an MCU.
The MCP3914 includes advanced security features to
secure the communications and the configuration set-
tings, such as a CRC-16 checksum on both serial data
outputs and static register map configuration. It also
includes a register map lock through an 8-bit secure key
to stop unwanted
WRITE
commands from processing.
The MCP3914 is capable of interfacing with a variety of
voltage and current sensors, including shunts, Current
Transformers, Rogowski coils and Hall effect sensors.
Package Type
MCP3914
(5x5 UQFN*)
RESET
30 SDI
29 SDO
28 SCK
27 CS
EP
41
26 OSC2
25 OSC1/CLKI
24 D
GND
23 NC
22 DR
21 D
GND
11 12 13 14 15 16 17 18 19 20
CH7+
REFIN+/
OUT
REFIN-
A
GND
CH6-
CH6+
CH7-
AV
DD
NC
DV
DD
CH1+
CH0+
A
GND
NC
DV
DD
AV
DD
CH1-
CH0-
D
GND
40 39 38 37 36 35 34 33 32 31
CH2+ 1
CH2- 2
CH3- 3
CH3+ 4
NC 5
NC 6
CH4+ 7
CH4- 8
CH5- 9
CH5+ 10
Applications:
•
•
•
•
•
•
Polyphase Energy Meters
Energy Metering and Power Measurement
Automotive
Portable Instrumentation
Medical and Power Monitoring
Audio/Voice Recognition
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
2013-2019 Microchip Technology Inc.
DS20005216B-page 1
MCP3914
Functional Block Diagram
REFIN+/OUT
AV
DD
Voltage
Reference
+
-
Vref- Vref+
OSR/2-
PHASE1 <11:0>
OFFCAL_CH0
<23:0>
GAINCAL_CH0
<23:0>
VREFEXT
DV
DD
AMCLK
Xtal Oscillator
Clock
Generation
MCLK
OSC1
OSC2
Vref
REFIN-
DMCLK/DRCLK
DMCLK
OSR<2:0>
PRE<1:0>
CH0+
CH0-
+
-
PGA
MOD<3:0>
)
Phase
Shifter
OSR/2
+
SINC +
SINC
1
3
X
Gain
Cal.
GAINCAL_CH1
<23:0>
DATA_CH0<23:0>
'6
Modulator
Offset
Cal.
OFFCAL_CH1
<23:0>
CH1+
CH1-
+
-
PGA
MOD<7:4>
)
Phase
Shifter
OSR/2-
PHASE1 <23:12>
+
SINC +
SINC
1
3
X
Gain
Cal.
GAINCAL_CH2
<23:0>
DATA_CH1<23:0>
'6
Modulator
Offset
Cal.
OFFCAL_CH2
<23:0>
CH2+
CH2-
+
-
PGA
MOD<11:8>
)
Phase
Shifter
OSR/2
+
SINC +
SINC
1
3
X
Gain
Cal.
GAINCAL_CH3
<23:0>
DATA_CH2<23:0>
'6
Modulator
Offset
Cal.
OFFCAL_CH3
<23:0>
CH3+
CH3-
+
-
PGA
MOD<15:12>
)
Phase
Shifter
SINC
3
+
SINC
1
+
Offset
Cal.
OFFCAL_CH4
<23:0>
X
Gain
Cal.
GAINCAL_CH4
<23:0>
DATA_CH3<23:0>
DR
SDO
Digital SPI
Interface
'6
Modulator
OSR/2-
PHASE0<11:0>
CH4+
CH4-
+
-
PGA
MOD<19:16>
)
Phase
Shifter
OSR/2
+
SINC +
SINC
1
3
X
Gain
Cal.
GAINCAL_CH5
<23:0>
RESET
SDI
SCK
CS
DATA_CH4<23:0>
'6
Modulator
Offset
Cal.
OFFCAL_CH5
<23:0>
CH5+
CH5-
+
-
PGA
MOD<23:20>
)
Phase
Shifter
SINC +
SINC
1
3
+
Offset
Cal.
OFFCAL_CH6
<23:0>
X
Gain
Cal.
GAINCAL_CH6
<23:0>
DATA_CH5<23:0>
'6
Modulator
OSR/2-
PHASE0<23:12>
CH6+
CH6-
+
-
PGA
MOD<27:24>
)
Phase
Shifter
OSR/2
+
SINC +
SINC
1
3
X
Gain
Cal.
GAINCAL_CH7
<23:0>
DATA_CH6<23:0>
'6
Modulator
Offset
Cal.
OFFCAL_CH7
<23:0>
CH7+
CH7-
+
-
PGA
MOD<31:28>
)
Phase
Shifter
SINC +
SINC
1
3
+
Offset
Cal.
X
Gain
Cal.
DATA_CH7<23:0>
'6
Modulator
POR
AV
DD
Monitoring
ANALOG
DIGITAL
POR
DV
DD
Monitoring
A
GND
D
GND
DS20005216B-page 2
2013-2019 Microchip Technology Inc.
MCP3914
1.0
ELECTRICAL
CHARACTERISTICS
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other condi-
tions, above those indicated in the operational listings
of this specification, is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
Absolute Maximum Ratings†
V
DD
..................................................................... -0.3V to 4.0V
Digital inputs and outputs w.r.t. A
GND
................. -0.3V to 4.0V
Analog input w.r.t. A
GND
..................................... ....-2V to +2V
V
REF
input w.r.t. A
GND
.............................. -0.6V to V
DD
+ 0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) ................. 1.5 kV, 300V
ESD on all other pins (HBM,MM) ...........................2 kV, 300V
1.1
Electrical Specifications
ANALOG SPECIFICATIONS
TABLE 1-1:
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V;
MCLK = 4 MHz; PRE[1:0] =
00;
OSR = 256; GAIN =
1;
VREFEXT =
0;
CLKEXT =
1;
DITHER[1:0] =
11;
BOOST[1:0] =
10;
V
CM
= 0V; T
A
= -40°C to +125°C; V
IN
= -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic
ADC Performance
Resolution
(no missing codes)
Sampling Frequency
Output Data Rate
f
S
(DMCLK)
f
D
(DRCLK)
24
—
—
—
1
4
—
4
125
bits
MHz
ksps
OSR = 256 or greater
For maximum condition,
BOOST[1:0] =
11
For maximum condition,
BOOST[1:0] =
11,
OSR = 32
All analog input channels,
measured to A
GND
RESET[7:0] =
11111111,
MCLK running continuously
V
REF
= 1.2V,
proportional to V
REF
Note 5
Sym
Min
Typ
Max
Units
Conditions
Analog Input Absolute
Voltage on CHn+/- Pins,
n Between 0 and 7
Analog Input
Leakage Current
Differential Input
Voltage Range
Offset Error
Offset Error Drift
Note 1:
CHn+/-
-1
—
+1
V
I
IN
—
±1
—
0.2
0.5
—
+600/GAIN
1
—
nA
mV
mV
µV/°C
(CH
n+
– CH
n-
) -600/GAIN
V
OS
-1
—
2:
3:
4:
5:
6:
7:
Dynamic performance specified at -0.5 dB below the maximum differential input value,
V
IN
= 1.2 V
PP
= 424 mV
RMS
@ 50/60 Hz, V
REF
= 1.2V. See
Section 4.0 “Terminology and Formulas”
for
definition. This parameter is established by characterization and not 100% tested.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[7:0] =
00000000,
RESET[7:0] =
00000000,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[7:0] =
11111111,
VREFEXT =
1,
CLKEXT =
1.
Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see
Figure 2-32
for individual channel performance).
Applies to all gains. Offset and gain errors depend on PGA gain setting; see
Section 2.0 “Typical
Performance Curves”
for typical performance.
Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in
Table 5-2,
as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2.
2013-2019 Microchip Technology Inc.
DS20005216B-page 3
MCP3914
TABLE 1-1:
ANALOG SPECIFICATIONS
(CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V;
MCLK = 4 MHz; PRE[1:0] =
00;
OSR = 256; GAIN =
1;
VREFEXT =
0;
CLKEXT =
1;
DITHER[1:0] =
11;
BOOST[1:0] =
10;
V
CM
= 0V; T
A
= -40°C to +125°C; V
IN
= -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic
Gain Error
Gain Error Drift
Integral Nonlinearity
Measurement Error
INL
ME
Sym
GE
Min
-4
—
—
—
Typ
—
1
5
0.1
Max
+4
—
—
—
Units
%
ppm/°C
ppm
%
Measured with a 10,000:1 dynamic
range (from 600 mV
Peak
to
60 µV
Peak
), AV
DD
= DV
DD
= 3V,
measurement points averaging
time: 20 seconds, measured on
each channel pair (CH0/1, CH2/3,
CH4/5 and CH6/7)
G = 1, proportional to 1/AMCLK
G = 2, proportional to 1/AMCLK
G = 4, proportional to 1/AMCLK
G = 8, proportional to 1/AMCLK
G = 16, proportional to 1/AMCLK
G = 32, proportional to 1/AMCLK
Note 5
Conditions
Differential Input
Impedance
Z
IN
232
142
72
38
36
33
—
—
—
—
—
—
94.5
-107
95
112
-122
-73
-73
-100
—
—
—
—
—
—
—
-103
—
—
—
—
—
—
k
k
k
k
k
k
dB
dBc
dB
dBFS
dB
dB
dB
dB
Signal-to-Noise and
Distortion Ratio
(Note
1)
Total Harmonic Distortion
(Note
1)
Signal-to-Noise Ratio
(Note
1)
Spurious Free Dynamic
Range
(Note
1)
Crosstalk (50, 60 Hz)
AC Power
Supply Rejection
DC Power
Supply Rejection
DC Common-mode
Rejection
Note 1:
SINAD
THD
SNR
SFDR
CTALK
AC PSRR
DC PSRR
DC CMRR
92
—
92
—
—
—
—
—
Includes the first 35 harmonics
Note 4
AV
DD
= DV
DD
= 3V + 0.6 V
PP
,
50/60 Hz, 100/120 Hz
AV
DD
= DV
DD
= 2.7V to 3.6V
V
CM
from -1V to +1V
2:
3:
4:
5:
6:
7:
Dynamic performance specified at -0.5 dB below the maximum differential input value,
V
IN
= 1.2 V
PP
= 424 mV
RMS
@ 50/60 Hz, V
REF
= 1.2V. See
Section 4.0 “Terminology and Formulas”
for
definition. This parameter is established by characterization and not 100% tested.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[7:0] =
00000000,
RESET[7:0] =
00000000,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[7:0] =
11111111,
VREFEXT =
1,
CLKEXT =
1.
Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see
Figure 2-32
for individual channel performance).
Applies to all gains. Offset and gain errors depend on PGA gain setting; see
Section 2.0 “Typical
Performance Curves”
for typical performance.
Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in
Table 5-2,
as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2.
DS20005216B-page 4
2013-2019 Microchip Technology Inc.
MCP3914
TABLE 1-1:
ANALOG SPECIFICATIONS
(CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V;
MCLK = 4 MHz; PRE[1:0] =
00;
OSR = 256; GAIN =
1;
VREFEXT =
0;
CLKEXT =
1;
DITHER[1:0] =
11;
BOOST[1:0] =
10;
V
CM
= 0V; T
A
= -40°C to +125°C; V
IN
= -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic
Internal Voltage Reference
Tolerance
Temperature Coefficient
V
REF
TCV
REF
1.176
—
1.2
9
1.224
—
V
VREFEXT =
0,
T
A
= +25°C only
ppm/°C T
A
= -40°C to +125°C,
VREFEXT =
0,
VREFCAL[7:0] = 0x50
k
µA
VREFEXT =
0
VREFEXT =
0,
SHUTDOWN[7:0] =
11111111
Sym
Min
Typ
Max
Units
Conditions
Output Impedance
Internal Voltage Reference
Operating Current
Voltage Reference Input
Input Capacitance
Differential Input Voltage
Range (V
REF
+ – V
REF
-)
Absolute Voltage on
REFIN+ Pin
Absolute Voltage
REFIN- Pin
Master Clock Input
Master Clock Input
Frequency Range
Crystal Oscillator Operating
Frequency Range
Analog Master Clock
Crystal Oscillator
Operating Current
Power Supply
Operating Voltage, Analog
Operating Voltage, Digital
Operating Current, Analog
(Note
2)
ZOUTV
REF
AI
DD
V
REF
—
—
0.6
54
—
—
—
V
REF
V
REF
+
V
REF
-
1.1
V
REF
- + 1.1
-0.1
—
—
—
—
10
1.3
V
REF
- + 1.3
+0.1
pF
V
V
V
VREFEXT =
1
VREFEXT =
1
REFIN- should be connected to
A
GND
when VREFEXT =
0
CLKEXT =
1
(Note
7)
CLKEXT =
0
(Note
7)
(Note
7)
CLKEXT =
0
f
MCLK
f
XTAL
AMCLK
DIDDXTAL
—
1
—
—
—
—
—
80
20
20
16
—
MHz
MHz
MHz
µA
AV
DD
DV
DD
I
DD,A
2.7
2.7
—
—
—
—
—
—
5.8
7.2
9.8
17.2
3.6
3.6
7.5
10
12.5
22
V
V
mA
mA
mA
mA
BOOST[1:0] =
00
BOOST[1:0] =
01
BOOST[1:0] =
10
BOOST[1:0] =
11
Note 1:
2:
3:
4:
5:
6:
7:
Dynamic performance specified at -0.5 dB below the maximum differential input value,
V
IN
= 1.2 V
PP
= 424 mV
RMS
@ 50/60 Hz, V
REF
= 1.2V. See
Section 4.0 “Terminology and Formulas”
for
definition. This parameter is established by characterization and not 100% tested.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[7:0] =
00000000,
RESET[7:0] =
00000000,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[7:0] =
11111111,
VREFEXT =
1,
CLKEXT =
1.
Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see
Figure 2-32
for individual channel performance).
Applies to all gains. Offset and gain errors depend on PGA gain setting; see
Section 2.0 “Typical
Performance Curves”
for typical performance.
Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in
Table 5-2,
as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2.
2013-2019 Microchip Technology Inc.
DS20005216B-page 5
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