IMPORTANT NOTICE
Dear customer,
As from August 2
nd
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - NXP B.V.
is replaced with
ST-NXP Wireless.
Copyright
- the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site
-
http://www.nxp.com
is replaced with
http://www.stnwireless.com
Contact information
- the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
, is now found at
http://www.stnwireless.com
under Contacts.
●
●
●
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
www.stnwireless.com
ISP1504A1; ISP1504C1
ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
Rev. 01 — 6 August 2007
Product data sheet
1. General description
The ISP1504A1; ISP1504C1 (ISP1504x1) is a Universal Serial Bus (USB) On-The-Go
(OTG) transceiver that is fully compliant with
Universal Serial Bus Specification Rev. 2.0,
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2
and
UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The ISP1504x1 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to the USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1504x1 can interface to devices with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1504x1 is available in TFBGA36 package.
2. Features
I
Fully complies with:
N
Universal Serial Bus Specification Rev. 2.0
N
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2
N
UTMI+ Low Pin Interface (ULPI) Specification Rev 1.1
I
Interfaces to host, peripheral and OTG device cores; optimized for portable devices or
system ASICs with built-in USB OTG device core
I
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N
Integrated 45
Ω ±
10 % high-speed termination resistors, 1.5 kΩ
±
5 % full-speed
device pull-up resistor, and 15 kΩ
±
5 % host termination resistors
N
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N
USB clock and data recovery to receive USB data at
±500
ppm
N
USB data synchronization from 60 MHz input to 480 MHz output during transmit
N
Insertion of stuff bits during transmit and discarding of stuff bits during receive
N
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I
Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
NXP Semiconductors
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
I
I
I
I
I
N
Supports external charge pump or 5 V V
BUS
switch
N
Complete control over bus resistors
N
Data line and V
BUS
pulsing session request methods
N
Integrated V
BUS
voltage comparators
N
Integrated cable (ID) detector
Highly optimized ULPI-compliant interface
N
60 MHz, 8-bit interface between the core and the transceiver
N
Integrated Phase-Locked Loop (PLL) supporting input clock frequency of 19.2 MHz
for ISP1504A1, and 26 MHz for ISP1504C1
N
Fully programmable ULPI-compliant register set
N
Internal Power-On Reset (POR) circuit
Flexible system integration and very low current consumption, optimized for portable
devices
N
Power-supply input range is 3.0 V to 4.5 V
N
Internal voltage regulator supplies 3.3 V and 1.8 V
N
Supports external V
BUS
charge pump or 5 V supply:
External V
BUS
source is controlled using the PSW_N pin; open-drain PSW_N
allows per-port or ganged power control
Digital FAULT input to monitor the external V
BUS
supply status
N
Pin CS_N/PWRDN 3-states the ULPI interface, allowing bus reuse for other
applications
N
Supports power-down mode when V
CC(I/O)
is not present or when
pin CS_N/PWRDN is HIGH
N
Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage
pins minimize crosstalk
N
Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization
N
Typical suspend current of 50
µA
N
Typical power-down current of 0.5
µA
Full industrial grade operating temperature range from
−40 °C
to +85
°C
ElectroStatic Discharge (ESD) compliance
N
JESD22-A114D 2 kV contact Human Body Model (HBM)
N
JESD22-A115-A 200 V Machine Model (MM)
N
JESD22-C101-C 500 V Charge Device Model (CDM)
Available in a small TFBGA36 (3.5 mm
×
3.5 mm) Restriction of Hazardous
Substances (RoHS) compliant, halogen-free and lead-free package
3. Applications
I
I
I
I
Digital still camera
Digital TV
Digital Versatile Disc (DVD) recorder
External storage device, for example:
N
Zip drive
N
Magneto-Optical (MO) drive
N
Optical drive: CD-ROM, CD-RW, CD-DVD
© NXP B.V. 2007. All rights reserved.
ISP1504A1_ISP1504C1_1
Product data sheet
Rev. 01 — 6 August 2007
2 of 80
NXP Semiconductors
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
I
I
I
I
I
I
I
Mobile phone
MP3 player
PDA
Printer
Scanner
Set-Top Box (STB)
Video camera
4. Ordering information
Table 1.
Part
Type number
ISP1504A1ET
ISP1504C1ET
[1]
Ordering information
Package
Marking
504M
[1]
504P
[1]
Crystal or clock Name
frequency
19.2 MHz
26 MHz
Description
Version
SOT912-1
TFBGA36 plastic thin fine-pitch ball grid array package;
36 balls; body 3.5
×
3.5
×
0.8 mm
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1504A1_ISP1504C1_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2007
3 of 80
NXP Semiconductors
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
5. Block diagram
CLOCK
A4
B1, A1,
A2, A3,
A5, A6,
B6, C6
USB DATA
SERIALIZER
HI-SPEED USB ATX
ULPI
INTERFACE
CONTROLLER
D1
DP
ULPI
interface
DATA
[7:0]
8
DIR
STP
NXT
E5
D6
D5
REGISTER
MAP
USB DATA
DESERIALIZER
TERMINATION
RESISTORS
C1
DM
V
BUS
valid external
ON-THE-GO MODULE
Drive V
BUS
external
ID
DETECTOR
D3
ID
USB
cable
CS_N/PWRDN
RESET_N
C3
C4
POWER-ON
RESET
global
reset
V
BUS
COMPARATORS
F4
SRP CHARGE
AND DISCHARGE
RESISTORS
V
BUS
PLL
global clocks
XTAL1
XTAL2
F5
F6
CRYSTAL
OSCILLATOR
E2
FAULT
PSW_N
V
CC(I/O)
B2, B3,
B5
interface voltage
internal power
ISP1504x1
D4
REG3V3
REG1V8
V
CC
E3
E6
V
REF
VOLTAGE
REGULATOR
B4, C5,
D2, E1, E4
BAND GAP
REFERENCE
VOLTAGE
C2
RREF
F3
004aaa942
GND
Fig 1. Block diagram
ISP1504A1_ISP1504C1_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2007
4 of 80
京公网安备 11010802033920号
EEWORLD
