MT42L128M32D1GU-25WT datasheet, PDF

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MT42L128M32D1GU-25WT: DescriptionDDR DRAM,; Categorystorage storage; File Size2MB，172 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT42L128M32D1GU-25WT Overview

DDR DRAM,

MT42L128M32D1GU-25WT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
Reach Compliance Code	compliant
Memory IC Type	DDR DRAM
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum time at peak reflow temperature	NOT SPECIFIED

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4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Mobile LPDDR2 SDRAM

MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,

MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,

MT42L256M64D4, MT42L384M32D3

Features

• Ultra low-voltage core and I/O power supplies

– V

DD2

= 1.14–1.30V

– V

DDCA

DDQ

= 1.14–1.30V

– V

DD1

= 1.70–1.95V

• Clock frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per-bank refresh for concurrent operation

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed Clock Rate Data Rate

Grade

(MHz)

(Mb/s/pin)

-18

-25

-3

533

400

333

1066

800

667

RCD/

Options

Marking

Typical

• V

DD2

: 1.2V

• Configuration

– 32 Meg x 16 x 8 banks x 1 die

256M16

– 16 Meg x 32 x 8 banks x 1 die

128M32

– 16 Meg x 32 x 8 banks x 2 die

256M32

– 1 (16 Meg x 32 x 8 banks) + 2 (32

384M32

Meg x 16 x 8 banks)

– 32 Meg x 16 x 8 banks x 4 die

512M32

– 16 Meg x 32 x 8 banks x 2 die

128M64

– 16 Meg x 32 x 8 banks x 3 die

192M64

– 16 Meg x 32 x 8 banks x 4 die

256M64

• Device type

– LPDDR2-S4, 1 die in package

– LPDDR2-S4, 2 die in package

– LPDDR2-S4, 3 die in package

– LPDDR2-S4, 4 die in package

• FBGA “green” package

– 134-ball FBGA (10mm x

GU, GV

11.5mm)

– 168-ball FBGA (12mm x 12mm)

LF, LG

– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,

– 220-ball FBGA (14mm x 14mm)

LD, MP

– 240-ball FBGA (14mm x 14mm)

– 253-ball FBGA (11mm x 11mm)

EU, EV

• Timing – cycle time

– 1.875ns @ RL = 8

-18

– 2.5ns @ RL = 6

-25

– 3.0ns @ RL = 5

-3

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +105°C

• Revision

Note:

1. For Fast

RCD/

RP, contact factory.

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Contents

General Description ....................................................................................................................................... 12

General Notes ............................................................................................................................................ 12

Specifications ........................................................................................................................................... 13

Package Block Diagrams ................................................................................................................................. 18

Package Dimensions ....................................................................................................................................... 24

Ball Assignments and Descriptions ................................................................................................................. 37

Functional Description ................................................................................................................................... 46

Power-Up ....................................................................................................................................................... 47

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 49

Power-Off ....................................................................................................................................................... 49

Uncontrolled Power-Off .............................................................................................................................. 50

Mode Register Definition ................................................................................................................................ 50

Mode Register Assignments and Definitions ................................................................................................ 50

ACTIVATE Command ..................................................................................................................................... 61

8-Bank Device Operation ............................................................................................................................ 61

Read and Write Access Modes ......................................................................................................................... 62

Burst READ Command ................................................................................................................................... 62

READs Interrupted by a READ ..................................................................................................................... 69

Burst WRITE Command .................................................................................................................................. 69

WRITEs Interrupted by a WRITE ................................................................................................................. 72

BURST TERMINATE Command ...................................................................................................................... 72

Write Data Mask ............................................................................................................................................. 74

PRECHARGE Command ................................................................................................................................. 75

READ Burst Followed by PRECHARGE ......................................................................................................... 76

WRITE Burst Followed by PRECHARGE ....................................................................................................... 77

Auto Precharge ........................................................................................................................................... 78

READ Burst with Auto Precharge ................................................................................................................. 78

WRITE Burst with Auto Precharge ............................................................................................................... 79

REFRESH Command ...................................................................................................................................... 81

REFRESH Requirements ............................................................................................................................. 87

SELF REFRESH Operation ............................................................................................................................... 89

Partial-Array Self Refresh – Bank Masking .................................................................................................... 90

Partial-Array Self Refresh – Segment Masking .............................................................................................. 91

MODE REGISTER READ ................................................................................................................................. 92

Temperature Sensor ................................................................................................................................... 94

DQ Calibration ........................................................................................................................................... 96

MODE REGISTER WRITE Command ............................................................................................................... 98

MRW RESET Command .............................................................................................................................. 98

MRW ZQ Calibration Commands ................................................................................................................ 99

ZQ External Resistor Value, Tolerance, and Capacitive Loading .................................................................... 101

Power-Down ................................................................................................................................................. 101

Deep Power-Down ........................................................................................................................................ 108

Input Clock Frequency Changes and Stop Events ............................................................................................ 109

Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 109

Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 110

NO OPERATION Command ........................................................................................................................... 110

Simplified Bus Interface State Diagram ....................................................................................................... 110

Truth Tables .................................................................................................................................................. 112

Electrical Specifications ................................................................................................................................. 120

Absolute Maximum Ratings ....................................................................................................................... 120

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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