MT44K16M36RB-093E:B datasheet, PDF

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MT44K16M36RB-093E:B: DescriptionDDR DRAM, 16MX36, CMOS, PBGA168, FBGA-168; Categorystorage storage; File Size2MB，118 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT44K16M36RB-093E:B Overview

DDR DRAM, 16MX36, CMOS, PBGA168, FBGA-168

MT44K16M36RB-093E:B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
package instruction	TBGA,
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	11 weeks
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	S-PBGA-B168
JESD-609 code	e1
length	13.5 mm
memory density	603979776 bit
Memory IC Type	DDR DRAM
memory width	36
Number of functions	1
Number of ports	1
Number of terminals	168
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
organize	16MX36
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.42 V
Minimum supply voltage (Vsup)	1.28 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	13.5 mm

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576Mb: x18, x36 RLDRAM 3

Features

RLDRAM 3

MT44K32M18 – 2 Meg x 18 x 16 Banks

MT44K16M36 – 1 Meg x 36 x 16 Banks

Features

• 1066 MHz DDR operation (2133 Mb/s/ball data

rate)

• 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock

frequency)

• Organization

– 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)

– 16 banks

• 1.2V center-terminated push/pull I/O

• 2.5V V

EXT

, 1.35V V

, 1.2V V

DDQ

I/O

• Reduced cycle time (

RC (MIN) = 7.5 - 12ns)

• SDR addressing

• Programmable READ/WRITE latency (RL/WL) and

burst length

• Data mask for WRITE commands

• Differential input clocks (CK, CK#)

• Free-running differential input data clocks (DKx,

DKx#) and output data clocks (QKx, QKx#)

• On-die DLL generates CK edge-aligned data and

differential output data clock signals

• 64ms refresh (128K refresh per 64ms)

• 168-ball BGA package

• 40Ω or 60Ω matched impedance outputs

• Integrated on-die termination (ODT)

• Single or multibank writes

• Extended operating range (200–1066 MHz)

• READ training register

• Multiplexed and non-multiplexed addressing capa-

bilities

• Mirror function

• Output driver and ODT calibration

• JTAG interface (IEEE 1149.1-2001)

Options

• Clock cycle and

RC timing

– 0.93ns and

RC (MIN) = 7.5ns

(RL3-2133)

– 0.93ns and

RC (MIN) = 8ns

(RL3-2133)

– 1.07ns and

RC (MIN) = 8ns

(RL3-1866)

– 1.25ns and

RC (MIN) = 8ns

(RL3-1600)

– 1.25ns and

RC (MIN) = 10ns

(RL3-1600)

– 1.25ns and

RC (MIN) = 12ns

(RL3-1600)

• Configuration

– 32 Meg x 18

– 16 Meg x 36

• Operating temperature

– Commercial (T

= 0° to +95°C)

– Industrial (T

= –40°C to +95°C)

• Package

– 168-ball BGA (Pb-free)

• Revision

Note:

Marking

-093F

-093E

-107E

-125F

-125E

-125

32M18

16M36

None

:A / :B

1. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on www.micron.com for availa-

ble offerings.

09005aef84003617

576mb_rldram3.pdf - Rev. J 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

576Mb: x18, x36 RLDRAM 3

Features

Contents

General Description ......................................................................................................................................... 9

General Notes .............................................................................................................................................. 9

State Diagram ................................................................................................................................................ 10

Functional Block Diagrams ............................................................................................................................. 11

Ball Assignments and Descriptions ................................................................................................................. 13

Package Dimensions ....................................................................................................................................... 17

Electrical Characteristics – I

Specifications .................................................................................................. 18

Electrical Specifications – Absolute Ratings and I/O Capacitance ..................................................................... 25

Absolute Maximum Ratings ........................................................................................................................ 25

Input/Output Capacitance .......................................................................................................................... 25

AC and DC Operating Conditions .................................................................................................................... 26

AC Overshoot/Undershoot Specifications .................................................................................................... 27

Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 31

Slew Rate Definitions for Differential Input Signals ...................................................................................... 32

ODT Characteristics ....................................................................................................................................... 34

ODT Resistors ............................................................................................................................................ 35

ODT Sensitivity .......................................................................................................................................... 36

Output Driver Impedance ............................................................................................................................... 36

Output Driver Sensitivity ............................................................................................................................ 37

Output Characteristics and Operating Conditions ............................................................................................ 39

Reference Output Load ............................................................................................................................... 42

Slew Rate Definitions for Single-Ended Output Signals ..................................................................................... 43

Slew Rate Definitions for Differential Output Signals ........................................................................................ 44

Speed Bin Tables ............................................................................................................................................ 45

AC Electrical Characteristics ........................................................................................................................... 47

Temperature and Thermal Impedance Characteristics ..................................................................................... 53

Command and Address Setup, Hold, and Derating ........................................................................................... 55

Data Setup, Hold, and Derating ....................................................................................................................... 62

Commands .................................................................................................................................................... 69

MODE REGISTER SET (MRS) Command ......................................................................................................... 70

Mode Register 0 (MR0) .................................................................................................................................... 71

RC ............................................................................................................................................................. 71

Data Latency .............................................................................................................................................. 72

DLL Enable/Disable ................................................................................................................................... 72

Address Multiplexing .................................................................................................................................. 72

Mode Register 1 (MR1) .................................................................................................................................... 73

Output Drive Impedance ............................................................................................................................ 73

DQ On-Die Termination (ODT) ................................................................................................................... 73

DLL Reset ................................................................................................................................................... 73

ZQ Calibration ............................................................................................................................................ 74

ZQ Calibration Long ................................................................................................................................... 75

ZQ Calibration Short ................................................................................................................................... 75

AUTO REFRESH Protocol ............................................................................................................................ 76

Burst Length (BL) ....................................................................................................................................... 76

Mode Register 2 (MR2) .................................................................................................................................... 78

READ Training Register (RTR) ..................................................................................................................... 78

WRITE Protocol .......................................................................................................................................... 80

WRITE Command .......................................................................................................................................... 80

Multibank WRITE ....................................................................................................................................... 81

READ Command ............................................................................................................................................ 81

09005aef84003617

576mb_rldram3.pdf - Rev. J 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

576Mb: x18, x36 RLDRAM 3

Features

AUTO REFRESH Command ............................................................................................................................ 83

INITIALIZATION Operation ............................................................................................................................ 85

WRITE Operation ........................................................................................................................................... 87

READ Operation ............................................................................................................................................. 91

AUTO REFRESH Operation ............................................................................................................................. 94

RESET Operation ............................................................................................................................................ 97

Clock Stop ...................................................................................................................................................... 97

Mirror Function ............................................................................................................................................. 99

Multiplexed Address Mode ............................................................................................................................. 100

Data Latency in Multiplexed Address Mode ................................................................................................ 105

REFRESH Command in Multiplexed Address Mode .................................................................................... 105

IEEE 1149.1 Serial Boundary Scan (JTAG) ....................................................................................................... 109

Disabling the JTAG Feature ........................................................................................................................ 109

Test Access Port (TAP) ................................................................................................................................ 109

TAP Controller ........................................................................................................................................... 110

Performing a TAP RESET ............................................................................................................................ 112

TAP Registers ............................................................................................................................................ 112

TAP Instruction Set .................................................................................................................................... 113

09005aef84003617

576mb_rldram3.pdf - Rev. J 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

576Mb: x18, x36 RLDRAM 3

Features

List of Figures

Figure 1: 576Mb RLDRAM

3 Part Numbers ..................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................. 10

Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 11

Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 12

Figure 5: 168-Ball BGA ................................................................................................................................... 17

Figure 6: Single-Ended Input Signal ............................................................................................................... 27

Figure 7: Overshoot ....................................................................................................................................... 28

Figure 8: Undershoot .................................................................................................................................... 28

Figure 9: V

for Differential Signals ................................................................................................................ 29

Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 30

Figure 11: Definition of Differential AC Swing and

DVAC ................................................................................ 30

Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 32

Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 33

Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 34

Figure 15: Output Driver ................................................................................................................................ 37

Figure 16: DQ Output Signal .......................................................................................................................... 41

Figure 17: Differential Output Signal .............................................................................................................. 42

Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 42

Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 43

Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 44

Figure 21: Example Temperature Test Point Location ...................................................................................... 54

Figure 22: Nominal Slew Rate and

VAC for

IS (Command and Address - Clock) ............................................... 58

Figure 23: Nominal Slew Rate for

IH (Command and Address - Clock) ............................................................ 59

Figure 24: Tangent Line for

IS (Command and Address - Clock) ...................................................................... 60

Figure 25: Tangent Line for

IH (Command and Address - Clock) ..................................................................... 61

Figure 26: Nominal Slew Rate and

VAC for

DS (DQ - Strobe) .......................................................................... 65

Figure 27: Nominal Slew Rate for

DH (DQ - Strobe) ........................................................................................ 66

Figure 28: Tangent Line for

DS (DQ - Strobe) ................................................................................................. 67

Figure 29: Tangent Line for

DH (DQ - Strobe) ................................................................................................ 68

Figure 30: MRS Command Protocol ............................................................................................................... 70

Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 71

Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 73

Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 75

Figure 34: Read Burst Lengths ........................................................................................................................ 77

Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 78

Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 79

Figure 37: WRITE Command ......................................................................................................................... 80

Figure 38: READ Command ........................................................................................................................... 82

Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 83

Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 84

Figure 41: Power-Up/Initialization Sequence ................................................................................................. 86

Figure 42: WRITE Burst ................................................................................................................................. 87

Figure 43: Consecutive WRITE Bursts ............................................................................................................. 88

Figure 44: WRITE-to-READ ............................................................................................................................ 88

Figure 45: WRITE - DM Operation .................................................................................................................. 89

Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 89

Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 90

Figure 48: Basic READ Burst .......................................................................................................................... 91

Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 92

Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 92

09005aef84003617

576mb_rldram3.pdf - Rev. J 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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