®
ISL55100A
Data Sheet
November 24, 2008
FN7486.2
Quad 18V Pin Electronics Driver/Window
Comparator
The ISL55100A is a Quad pin driver and window comparator
fabricated in a wide voltage CMOS process. It is designed
specifically for Test During Burn In (TDBI) applications,
where cost, functional density, and power are all at a
premium.
This IC incorporates four channels of programmable drivers
and window comparators into a small 72 Ld QFN package.
Each channel has independent driver levels, data, and high
impedance control. Each receiver has dual comparators
which provide high and low threshold levels.
The ISL55100A uses differential mode digital inputs, and can
therefore mate directly with LVDS or CML outputs. Single
ended logic families are handled by connecting one of the
digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility). The comparator outputs are
single-ended, and the output levels are user defined to mate
directly with any digital technology.
The 18V driver output and receiver input ranges allow this
device to interface directly with TTL, ECL, CMOS (3V, 5V,
and 7V), LVCMOS, and custom level circuitry, as well as the
high voltage (Super Voltage) level required for many special
test modes for Flash Devices.
Features
• Low Driver Output Resistance
- R
OUT
Maximum: ISL55100A 7.0Ω
• 18V I/O Range
• 50MHz Operation
• 4-Channel Driver/Receiver Pairs with Per Pin Flexibility
• Dual Level - Per Pin - Input Thresholds
• Differential or Single-Ended Digital Inputs
• User Defined Comparator Output Levels
• Low Channel-to-Channel Timing Skew
• Small Footprint (72 Ld QFN)
• Pb-Free (RoHS Compliant)
Applications
• Burn In ATE
• Wafer Level Flash Memory Test
• LCD Panel Test
• Low Cost ATE
• Instrumentation
• Emulation
Functional Block Diagram
QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS
VH(0:3)
DATA+(0:3)
DATA-(0:3)
DRVEN+(0:3)
+
-
DRVEN-(0:3)
QUAD - DUAL LEVEL COMPARATOR - RECEIVERS
COMP HIGH
QA(0:3)
COMP LOW
V
EE
COMP HIGH
QB(0:3)
COMP LOW
V
EE
V
CC
+
-
VINP(0:3)
V
CC
+
-
+
-
DOUT(0:3)
VL(0:3)
• Device Programmers
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
72 Ld QFN
PKG.
DWG. #
L72.10x10
ISL55100AIRZ* ISL55100 AIRZ
CVA(0:3)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CVB(0:3)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL55100A
Pinout
ISL55100A
(72 LD QFN)
TOP VIEW
DRV EN+ 0
DRV EN- 0
QA 0
QB 0
VCC
VEE
V
CC
V
CC
V
EE
V
EE
NC
NC
NC
NC
NC
NC
NC
56
72
DATA+ 0
DATA- 0
QA 1
QB 1
DRV EN+ 1
DRV EN- 1
DATA+ 1
DATA- 1
QA 2
QB 2
DRV EN+ 2
DRV EN- 2
DATA+ 2
DATA- 2
QA 3
QB 3
DRV EN+ 3
DRV EN- 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DATA+ 3
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
NC
55
54 V
EXT
53 VH 0
52 DOUT 0
51 NC
50 VL 0
49 VH 1
48 DOUT 1
47 NC
46 VL 1
45 VH 2
44 DOUT 2
43 NC
42 VL 2
41 VH 3
40 DOUT 3
39 NC
38 VL 3
37 LOWSWING
36
VINP 3
20
DATA- 3
21
CVA 0
22
VINP 0
23
CVB 0
24
COMP HIGH
25
COMP LOW
26
V
EE
27
V
CC
28
CVA 1
29
VINP 1
30
CVB 1
31
CVA 2
32
VINP 2
33
CVB 2
34
CVA 3
35
CVB 3
2
FN7486.2
November 24, 2008
ISL55100A
Pin Descriptions
PIN
DATA+(0:3)
DATA-(0:3)
FUNCTION
Positive differential digital input that determines the driver output state when it is enabled.
Negative differential digital input that determines the driver output state when it is enabled.
DRV EN+(0:3) Positive differential digital input that enables or disables the corresponding driver.
DRV EN-(0:3) Negative differential digital input that enables or disables the corresponding driver.
QA (0:3)
QB (0:3)
DOUT (0:3)
VINP (0:3)
VH (0:3)
VL (0:3)
NC
CVA (0:3)
CVB (0:3)
COMP HI
COMP LO
V
CC
V
EE
V
EXT
LOWSWING
Comparator digital outputs. QA(X) is high when VINP(X) exceeds CVA(X).
Comparator digital outputs. QB(X) is high when VINP(X) exceeds CVB(X).
Driver outputs.
Comparator inputs.
Unbuffered analog inputs that set each individual driver’s “high” voltage level.
Unbuffered analog inputs that set each individual driver’s “low” voltage level. VL must be a lower voltage than VH.
No internal connection.
Analog inputs that set the threshold for the corresponding Channel’s A comparators.
Analog inputs that set the threshold for the corresponding Channel’s B comparators.
Supply voltage, unbuffered input that sets the high output level of all comparators. Must be greater than COMP LO.
Supply voltage, unbuffered input that sets the low output level of all comparators. Must be less than COMP HI.
Positive power supply (5% tolerance).
Negative power supply (5% tolerance).
External 5.5VDC power supply (5.5VDC to 6.0VDC as
referenced to V
EE
, NOT GND. Recommended V
EXT
= 5.5V) for internal
logic. Connect pin to V
EE
when not using an external supply.
Input that selects driver output configurations optimized to yield minimum overshoots for low level swings (VH < V
EE
+5V), or
optimized for large output swings. Connect LOWSWING to V
EE
to select low swing circuitry, or connect it to V
CC
to select high
swing circuitry.
Truth Tables
DRIVERS
INPUTS
DATA
X
+>-
+<-
X = DON’T CARE
DRV EN
+>-
+<-
+<-
OUTPUT
DOUT
Hi - Z
VH
VL
<CVA
<CVA
>CVA
>CVA
INPUT
VINP
RECEIVERS
OUTPUTS
QA
<CVB
>CVB
<CVB
>CVB
0
0
1
1
QB
0
1
0
1
3
FN7486.2
November 24, 2008
ISL55100A
Absolute Maximum Ratings
V
CC
to V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V
V
EXT
to V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Input Voltages
DATA, DRV EN, CVX, VH, VL, VINP, COMPX, LOWSWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
EE
- 0.5V) to (V
CC
+ 0.5V)
Output Voltages
DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . (VL - 0.5V) to (VH + 0.5V)
QX . . . . . . . . . . . . (COMP LOW - 0.5V) to (COMP HIGH + 0.5V)
Thermal Information
Thermal Resistance (Typical, Notes 1, 2)
θ
JA
(°C/W)
θ
JC
(°C/W)
72 Ld QFN Package. . . . . . . . . . . . . . . 23
2.0
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power Dissipation Considerations” on page 9 for
more information.
Recommended Operating Conditions
PARAMETER
Device Power-(V
EXT
= V
EE)
V
EXT
Not
Used
Device Power-(V
EXT
= V
EE
+ 5.5V)
V
EXT
Optional External Logic Power
Driver Output High Rail
Driver Output Low Rail
Comparator Output High Rail
Comparator Output Low Rail
Ambient Temperature
Junction Temperature
SYMBOL
V
CC
- V
EE
V
CC
- V
EE
V
EXT
- V
EE
V
H
V
L
COMP-High
COMP-Low
T
A
T
J
MIN
(Note 10)
12 (Note 7)
9 (Note 7)
5.5 (Note 7)
V
EE
+ 1
V
EE
+ 0.5
V
EE
+ 1
V
EE
+ 0.5
-40
-
TYP
15
15
5.75
-
-
-
-
-
-
MAX
(Note 10)
18
18
6.0
V
CC
- 0.5
V
EE
+ 6
V
CC
- 0.5
V
EE
+ 6
+85
+150
UNITS
V
V
V
V
V
V
V
°C
°C
Electrical Specifications
PARAMETER
DRIVER DC CHARACTERISTICS
ISL55100A Output Resistance
ISL55100A DC Output Current
Test Conditions: V
CC
= 12V, V
EE
= -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp-Low = 0V, V
5V
= V
EE
and
LOWSWING = V
CC
.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
R
OUTD
I
OUTD
I
OUTDAC
V
OMIN
HIZ
I
O
= ±200mA, data not toggling
Per Individual driver
Per Individual driver
V
H
= 200mV, V
L
= 0V
V
OUT
= V
CC
with V
H
= V
L
+ V
EE
or
V
OUT
= VEE with V
H
= V
L
= V
CC
3
±200
-
185
-1
4.5
-
1.0
-
0
7.0
-
-
-
1
Ω
mA
A
mV
µA
ISL55100A AC Output Current (Note 3)
ISL55100A Minimum Output Swing
Disabled HIZ Leakage Current
DRIVER TIMING CHARACTERISTICS
Data± to DOUT Propagation Delay
t
PD
Lowswing Disabled (Note 6)
Lowswing Enabled (Note 6)
8
9
-
12
13
<1
18
16
17
-
26
ns
ns
ns
ns
Driver Timing Skew, All Edges (Note 4)
Disable (HIZ) Time
t
DIS
DVREN± Transition from Enable to
Disable
16
4
FN7486.2
November 24, 2008
ISL55100A
Electrical Specifications
PARAMETER
Enable Time
Test Conditions: V
CC
= 12V, V
EE
= -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp-Low = 0V, V
5V
= V
EE
and
LOWSWING = V
CC
.
(Continued)
SYMBOL
t
EN
TEST CONDITIONS
DVREN± Transition from Disable to
Enable: Lowswing Disabled (Note 6)
DVREN± Transition from Disable to
Enable: Lowswing Enabled (Note 6)
ISL55100A Rise/Fall Times (Note 4)
t
R
, t
F
100pF Load
ΔV
= 0.4V (20% to 80%)
ΔV
= 1V (20% to 80%)
ΔV
= 5V (10% to 90%)
ΔV
= 10V (10% to 90%)
ΔV
= 14V (10% to 90%)
ISL55100A Rise/Fall Times (Note 4)
t
R
, t
F
1000pF Load
ΔV
= 1V (20% to 80%)
ΔV
= 5V (10% to 90%)
ΔV
= 10V (10% to 90%)
ISL55100A Maximum Toggle Frequency
ISL55100A Min Driver Pulse Width
ISL55100A Overshoot Lowswing Mode
(Note 4)
FMAXD
t
WIDD
OS
No Load, 50% Symmetry
Standard Load, 1k/100pF (Note 5)
Lowswing Enabled, (VH - VL < 2V)
MIN
13
13
-
-
-
-
-
-
-
-
50
-
-
TYP
15
18
2.5
2.5
2.5
2.5
2.5
8.0
10.0
14.0
65
7.7
20mV+
10% of
output
swing
MAX
23
23
-
-
-
-
-
-
-
-
-
−
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
%+V
RECEIVER DC CHARACTERISTICS
Input Offset Voltage
Input Bias Current
Output Resistance
RECEIVER TIMING CHARACTERISTICS
Propagation Delay
Maximum Operating Frequency
Minimum Pulse Width
Rcvr Channel-to-Channel Skew (Note 4)
DIGITAL INPUTS
Differential Input High Voltage
Differential Input Low Voltage
Input Current
Common Mode Input Voltage Range
V
DIFFH
V
DIFFL
I
IN
V
CM
V
DIG+
- V
DIG-
V
DIG+
- V
DIG-
V
IN
= V
CC
or V
EE
V
DIFFL
> V
DIFFH
- 0.2V
V
DIFFH
< V
DIFFL
+ 0.2V
V
EE
+
0.2V
-
200
-
-50
-
-
0
-
-200
50
V
CC
- 5V
-
mV
mV
nA
V
V
t
PP
F
MAXR
t
WIDR
Under No Load, PWOUT Symmetry 50%
7
50
-
-
12
65
7.7
<1
18
-
-
-
ns
MHz
ns
ns
V
OS
I
BIAS
R
OUTR
CVA = CVB = 1.5V
V
INP
- CV
(A/B)
= ±5V
-50
-
18
-
10
25
50
30
35
mV
nA
Ω
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS V
EXT
= V
EE,
EXTERNAL LOGIC POWER OPTION NOT USED. (Notes 7, 8)
Positive Supply Current
Negative Supply Current
V
EXT
Supply Current
I
CC
I
EE
I
EXT
V
CC
= V
H
= 12V, V
EE
= V
L
= -3V,
V
EXT
= V
EE
, Outputs Unloaded
V
CC
= V
H
= 12V, V
EE
= V
L
= -3V,
V
EXT
= V
EE
, Outputs Unloaded
V
CC
= V
H
= 12, V
EE
= V
L
= -3V,
V
EXT
= V
EE
, Outputs Unloaded
-
-85
-
65
-65
<1
85
-
-
mA
mA
mA
5
FN7486.2
November 24, 2008
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