2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories
Data Sheet
FEATURES:
• Organized as 128K x16 / 256K x16 / 512K x16
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF200A/400A/800A
– 2.7-3.6V for SST39VF200A/400A/800A
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 55 ns for SST39LF200A/400A/800A
– 70 ns for SST39VF200A/400A/800A
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39LF/VF200A
4 seconds (typical) for SST39LF/VF400A
8 seconds (typical) for SST39LF/VF800A
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
– 48-bump XFLGA (4mm x 6mm) – 4 and 8Mbit
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are 128K x16 / 256K x16 / 512K x16 CMOS
Multi-Purpose Flash (MPF) manufactured with SST propri-
etary, high-performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply.
The SST39VF200A/400A/800A write (Program or Erase)
with a 2.7-3.6V power supply. These devices conform to
JEDEC standard pinouts for x16 memories.
Featuring
high-performance
Word-Program,
the
SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices provide a typical Word-Program time of 14
µsec. The devices use Toggle Bit or Data# Polling to detect
the completion of the Program or Erase operation. To pro-
tect against inadvertent write, they have on-chip hardware
and software data protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, they
significantly improve performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. When programming a flash device, the total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
©2010 Silicon Storage Technology, Inc.
S71117-12-000
04/10
1
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
To meet surface mount requirements, the SST39LF200A/
400A/800A and SST39VF200A/400A/800A are offered in
48-lead TSOP packages and 48-ball TFBGA packages as
well as Micro-Packages. See Figures 2, 3, and 4 for pin
assignments.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39LF200A/400A/800A and
SST39VF200A/400A/800A offers both Sector-Erase and
Block-Erase mode. The sector architecture is based on
uniform sector size of 2 KWord. The Block-Erase mode is
based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 11 and 12 for
timing waveforms. Any commands issued during the Sec-
tor- or Block-Erase operation are ignored.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF200A/400A/800A and
SST39VF200A/400A/800A is controlled by CE# and OE#,
both have to be low for the system to obtain data from the
outputs. CE# is used for device selection. When CE# is
high, the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 5).
Chip-Erase Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the “1” state. This
is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 10 for timing diagram,
and Figure 21 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Word-Program Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A are programmed on a word-by-word basis. Before
programming, the sector where the word exists must be
fully erased. The Program operation is accomplished in
three steps. The first step is the three-byte load sequence
for Software Data Protection. The second step is to load
word address and word data. During the Word-Program
operation, the addresses are latched on the falling edge of
either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever
occurs first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE# or
CE#, whichever occurs first. The Program operation, once
initiated, will be completed within 20 µs. See Figures 6 and
7 for WE# and CE# controlled Program operation timing
diagrams and Figure 18 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Write Operation Status Detection
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide two software means to detect the completion
of a write (Program or Erase) cycle, in order to optimize the
system write cycle time. The software detection includes
two status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
).
The End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
©2010 Silicon Storage Technology, Inc.
S71117-12-000
04/10
2
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide both hardware and software features to pro-
tect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Data# Polling (DQ
7
)
When the SST39LF200A/400A/800A and SST39VF200A/
400A/800A are in the internal Program operation, any
attempt to read DQ
7
will produce the complement of the
true data. Once the Program operation is completed, DQ
7
will produce true data. Note that even though DQ
7
may
have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear
in subsequent successive Read cycles after an interval of
1 µs. During internal Erase operation, any attempt to read
DQ
7
will produce a ‘0’. Once the internal Erase operation
is completed, DQ
7
will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 8 for Data# Polling timing diagram
and Figure 19 for a flowchart.
Software Data Protection (SDP)
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide the JEDEC approved Software Data Protec-
tion scheme for all data alteration operations, i.e., Program
and Erase. Any Program operation requires the inclusion of
the three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte sequence. This group of
devices are shipped with the Software Data Protection per-
manently enabled. See Table 4 for the specific software
command codes. During SDP command sequence, invalid
commands will abort the device to Read mode within TRC.
The contents of DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other
value, during any SDP command sequence.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle
Bit timing diagram and Figure 19 for a flowchart.
Common Flash Memory Interface (CFI)
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A also contain the CFI information to describe the char-
acteristics of the device. In order to enter the CFI Query
mode, the system must write three-byte sequence, same
as Software ID Entry command with 98H (CFI Query com-
mand) to address 5555H in the last byte sequence. Once
the device enters the CFI Query mode, the system can
read CFI data at the addresses given in Tables 5 through 9.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
©2010 Silicon Storage Technology, Inc.
S71117-12-000
04/10
3
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Product Identification
The Product Identification mode identifies the devices as
the SST39LF/VF200A, SST39LF/VF400A and SST39LF/
VF800A and manufacturer as SST. This mode may be
accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple
manufacturers in the same socket. For details, see Table 4
for software operation, Figure 13 for the Software ID Entry
and Read timing diagram, and Figure 20 for the Software
ID Entry command sequence flowchart.
TABLE 1: Product Identification
Address
Manufacturer’s ID
Device ID
SST39LF/VF200A
SST39LF/VF400A
SST39LF/VF800A
0001H
0001H
0001H
2789H
2780H
2781H
T1.3 1117
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 15 for timing waveform, and Figure 20 for a
flowchart.
Data
00BFH
0000H
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
DQ
15
- DQ
0
1117 B1.2
Control Logic
I/O Buffers and Data Latches
FIGURE 1: Functional Block Diagram
©2010 Silicon Storage Technology, Inc.
S71117-12-000
04/10
4
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
SST39LF/VF800A SST39LF/VF400A SST39LF/VF200A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SST39LF/VF200A SST39LF/VF400A SST39LF/VF800A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Standard Pinout
Top View
Die Up
1117 48-tsop P01.2
FIGURE 2: Pin Assignments for 48-Lead TSOP
TOP VIEW (balls facing down)
SST39LF/VF200A
6
5
4
3
2
1
A13 A12 A14
A9
A8
A10
NC
NC
A6
A2
A15 A16 NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6
NC DQ5 DQ12 VDD DQ4
1117 48-tfbga P02_2.0
WE# NC
NC
A7
A3
NC
NC
A4
NC DQ2 DQ10 DQ11 DQ3
A5
A1
DQ0 DQ8 DQ9 DQ1
A0 CE# OE# VSS
A
TOP VIEW (balls facing down)
B
C
D
E
F
G
H
TOP VIEW (balls facing down)
SST39LF/VF400A
SST39LF/VF800A
6
5
4
3
2
1
A13 A12 A14
A9
A8
A10
NC
NC
A6
A2
A15 A16 NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6
NC DQ5 DQ12 VDD DQ4
1117 48-tfbga P02_4.0
6
5
4
3
2
1
A13 A12 A14
A9
A8
A10
NC
A18
A6
A2
A15 A16 NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6
NC DQ5 DQ12 VDD DQ4
1117 48-tfbga P02_8.0
WE# NC
NC
A7
A3
NC
A17
A4
WE# NC
NC
A7
A3
NC
A17
A4
NC DQ2 DQ10 DQ11 DQ3
A5
A1
DQ0 DQ8 DQ9 DQ1
A0 CE# OE# VSS
NC DQ2 DQ10 DQ11 DQ3
A5
A1
DQ0 DQ8 DQ9 DQ1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
FIGURE 3: Pin Assignments for 48-Ball TFBGA
©2010 Silicon Storage Technology, Inc.
S71117-12-000
04/10
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
