AT25DF081A-SH-T datasheet, PDF

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AT25DF081A-SH-T: Description8M X 1 FLASH 2.7V PROM, PDSO8; Categorystorage storage; File Size988KB，53 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT25DF081A-SH-T Overview

8M X 1 FLASH 2.7V PROM, PDSO8

AT25DF081A-SH-T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOP, SOP8,.3
Contacts	8
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum clock frequency (fCLK)	100 MHz
Data retention time - minimum	20
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	5.29 mm
memory density	8388608 bi
Memory IC Type	FLASH
memory width	1
Number of functions	1
Number of terminals	8
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX1
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	2.16 mm
Serial bus type	SPI
Maximum standby current	0.00001 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
type	NOR TYPE
width	5.24 mm
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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Features

•

Single 2.7V - 3.6V Supply

•

Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3

– Supports RapidS Operation

– Supports Dual-Input Program and Dual-Output Read

Very High Operating Frequencies

– 100MHz for RapidS

– 85MHz for SPI

– Clock-to-Output (t

) of 5ns Maximum

Flexible, Optimized Erase Architecture for Code + Data Storage Applications

– Uniform 4-Kbyte Block Erase

– Uniform 32-Kbyte Block Erase

– Uniform 64-Kbyte Block Erase

– Full Chip Erase

Individual Sector Protection with Global Protect/Unprotect Feature

– 16 Sectors of 64-Kbytes Each

Hardware Controlled Locking of Protected Sectors via WP Pin

Sector Lockdown

– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only

128-Byte Programmable OTP Security Register

Flexible Programming

– Byte/Page Program (1- to 256-Bytes)

Fast Program and Erase Times

– 1.0ms Typical Page Program (256 Bytes) Time

– 50ms Typical 4-Kbyte Block Erase Time

– 250ms Typical 32-Kbyte Block Erase Time

– 400ms Typical 64-Kbyte Block Erase Time

Automatic Checking and Reporting of Erase/Program Failures

Software Controlled Reset

JEDEC Standard Manufacturer and Device ID Read Methodology

Low Power Dissipation

– 5mA Active Read Current (Typical at 20MHz)

– 5µA Deep Power-Down Current (Typical)

Endurance: 100,000 Program/Erase Cycles

Data Retention: 20 Years

Complies with Full Industrial Temperature Range

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (150-mil and 208-mil wide)

– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)

•

8-Mbit

2.7V Minimum

Serial Peripheral

Interface Serial

Flash Memory

Atmel AT25DF081A

Preliminary

•

8715B–SFLSH–8/10

Description

The Atmel

AT25DF081A is a serial interface Flash memory device designed for use in a wide variety of high-vol-

ume consumer based applications in which program code is shadowed from Flash memory into embedded or

external RAM for execution. The flexible erase architecture of the AT25DF081A, with its erase granularity as small

as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM

devices.

The physical sectoring and the erase block sizes of the AT25DF081A have been optimized to meet the needs of

today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the

memory space can be used much more efficiently. Because certain code modules and data storage segments

must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with

large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space

efficiency allows additional code routines and data storage segments to be added while still maintaining the same

overall device density.

The AT25DF081A also offers a sophisticated method for protecting individual sectors against erroneous or mali-

cious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system

can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array

securely protected. This is useful in applications where program code is patched or updated on a subroutine or

module basis, or in applications where data storage segments need to be modified without running the risk of

errant modifications to the program code segments. In addition to individual sector protection capabilities, the

AT25DF081A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be

either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors

do not have to be unprotected one-by-one prior to initial programming.

To take code and data protection to the next level, the AT25DF081A incorporates a sector lockdown mechanism

that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.

This addresses the need of certain secure applications that require portions of the Flash memory array to be per-

manently protected against malicious attempts at altering program code, data modules, security information, or

encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time Pro-

grammable) Security Register that can be used for purposes such as unique device serialization, system-level

Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in 3-volt systems, the AT25DF081A supports read, program, and erase operations

with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.

Atmel AT25DF081A [Preliminary]

8715B–SFLSH–8/10

Atmel AT25DF081A [Preliminary]

Pin Descriptions and Pinouts

Pin Descriptions

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted,

the device will be deselected and normally be placed in standby mode (not Deep Power-

Down mode), and the SO pin will be in a high-impedance state. When the device is

deselected, data will not be accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation

such as a program or erase cycle, the device will not enter the standby mode until the

completion of the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the

flow of data to and from the device. Command, address, and input data present on the SI pin

is always latched in on the rising edge of SCK, while output data on the SO pin is always

clocked out on the falling edge of SCK.

SERIAL INPUT (SERIAL INPUT/OUTPUT):

The SI pin is used to shift data into the device.

The SI pin is used for all data input including command and address sequences. Data on the

SI pin is always latched in on the rising edge of SCK.

With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow

two bits of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To

maintain consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout

the document with exception to sections dealing with the Dual-Output Read Array command

in which it will be referenced as SIO.

Data present on the SI pin will be ignored whenever the device is deselected (CS is

deasserted).

SERIAL OUTPUT (SERIAL OUTPUT/INPUT):

The SO pin is used to shift data out from the

device. Data on the SO pin is always clocked out on the falling edge of SCK.

With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to

allow two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK.

To maintain consistency with SPI nomenclature, the SOI pin will be referenced as SO

throughout the document with exception to sections dealing with the Dual-Input Byte/Page

Program command in which it will be referenced as SOI.

The SO pin will be in a high-impedance state whenever the device is deselected (CS is

deasserted).

WRITE PROTECT:

The WP pin controls the hardware locking feature of the device. Please

refer to

“Protection Commands and Features” on page 17

for more details on protection

features and the WP pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection

will not be used. However, it is recommended that the WP pin also be externally connected

to V

whenever possible.

HOLD:

The HOLD pin is used to temporarily pause serial communication without

deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK

pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold

condition to start. A Hold condition pauses serial communication only and does not have an

effect on internally self-timed operations such as a program or erase cycle. Please refer to

“Hold” on page 41

for additional details on the Hold operation.

The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be

used. However, it is recommended that the HOLD pin also be externally connected to V

whenever possible.

Asserted

State

Type

Table 2-1.

Symbol

Low

Input

SCK

Input

SI (SIO)

Input/Output

SO (SOI)

Output/Input

Low

Input

HOLD

Low

Input

8715B–SFLSH–8/10

AT25DF081A-SH-T Related Products

	AT25DF081A-SH-T	AT25DF081A	AT25DF081A-MH-T	AT25DF081A-MH-Y	AT25DF081A-SSH-T
Description	8M X 1 FLASH 2.7V PROM, PDSO8	8M X 1 FLASH 2.7V PROM, PDSO8	8M X 1 FLASH 2.7V PROM, PDSO8	8M X 1 FLASH 2.7V PROM, PDSO8	8M X 1 FLASH 2.7V PROM, PDSO8
memory width	1	1	1	1	1
Number of functions	1	1	1	1	1
Number of terminals	8	8	8	8	8
Maximum operating temperature	85 °C	85 Cel	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 Cel	-40 °C	-40 °C	-40 °C
organize	8MX1	8M × 1	8MX1	8MX1	8MX1
surface mount	YES	Yes	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	NO LEAD	NO LEAD	GULL WING
Terminal location	DUAL	pair	DUAL	DUAL	DUAL
Is it Rohs certified?	conform to	-	conform to	conform to	conform to
Parts packaging code	SOIC	-	SON	SON	SOIC
package instruction	SOP, SOP8,.3	-	VSON, SOLCC8,.25	VSON, SOLCC8,.25	SOP, SOP8,.25
Contacts	8	-	8	8	8
Reach Compliance Code	unknow	-	unknow	unknow	unknow
ECCN code	EAR99	-	EAR99	EAR99	EAR99
Maximum clock frequency (fCLK)	100 MHz	-	100 MHz	100 MHz	100 MHz
Data retention time - minimum	20	-	20	20	20
Durability	100000 Write/Erase Cycles	-	100000 Write/Erase Cycles	100000 Write/Erase Cycles	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G8	-	R-PDSO-N8	R-PDSO-N8	R-PDSO-G8
JESD-609 code	e4	-	e4	e4	e4
length	5.29 mm	-	6 mm	6 mm	4.925 mm
memory density	8388608 bi	-	8388608 bi	8388608 bi	8388608 bi
Memory IC Type	FLASH	-	FLASH	FLASH	FLASH
word count	8388608 words	-	8388608 words	8388608 words	8388608 words
character code	8000000	-	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	-	VSON	VSON	SOP
Encapsulate equivalent code	SOP8,.3	-	SOLCC8,.25	SOLCC8,.25	SOP8,.25
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	-	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE
Parallel/Serial	SERIAL	-	SERIAL	SERIAL	SERIAL
power supply	3/3.3 V	-	3/3.3 V	3/3.3 V	3/3.3 V
Programming voltage	2.7 V	-	2.7 V	2.7 V	2.7 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.16 mm	-	0.6 mm	0.6 mm	1.75 mm
Serial bus type	SPI	-	SPI	SPI	SPI
Maximum standby current	0.00001 A	-	0.00001 A	0.00001 A	0.00001 A
Maximum slew rate	0.02 mA	-	0.02 mA	0.02 mA	0.02 mA
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	-	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	-	3 V	3 V	3 V
technology	CMOS	-	CMOS	CMOS	CMOS
Terminal surface	NICKEL PALLADIUM GOLD	-	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal pitch	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm
type	NOR TYPE	-	NOR TYPE	NOR TYPE	NOR TYPE
width	5.24 mm	-	5 mm	5 mm	3.9 mm
write protect	HARDWARE/SOFTWARE	-	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE

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