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LTC2655BIUF-H16PBF

Description
Quad I²C 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference
File Size355KB,28 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
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LTC2655BIUF-H16PBF Overview

Quad I²C 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference

FEATURES
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LTC2655
Quad I
2
C 16-/12-Bit
Rail-to-Rail DACs with
10ppm/°C Max Reference
DESCRIPTION
The LTC
®
2655 is a family of Quad I
2
C 16-/12-Bit Rail-to-
Rail DACs with integrated 10ppm/°C max reference. The
DACs have built-in high performance, rail-to-rail, output
buffers and are guaranteed monotonic. The LTC2655-L
has a full-scale output of 2.5V with the integrated refer-
ence and operates from a single 2.7V to 5.5V supply.
The LTC2655-H has a full-scale output of 4.096V with
the integrated reference and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to 2 times the
external reference voltage.
The parts use the 2-wire I
2
C compatible serial interface.
The LTC2655 operates in both the standard mode (maxi-
mum clock rate of 100kHz) and the fast mode (maximum
clock rate of 400kHz). The LTC2655 incorporates a
power-on reset circuit that is controlled by the PORSEL
pin. If PORSEL is tied to GND the DACs power-on reset to
zero-scale. If PORSEL is tied to V
CC
, the DACs power-on
reset to mid-scale.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245, 6891433 and 7671770.
Integrated Reference 10ppm/°C Max
Maximum INL Error: ±4LSB at 16 Bits
Guaranteed Monotonic Over Temperature
Selectable Internal or External Reference
2.7V to 5.5V Supply Range (LTC2655-L)
Integrated Reference Buffers
Ultralow Crosstalk Between DACs (<1nV•s)
Power-On-Reset to Zero-Scale/Mid-Scale
Asynchronous DAC Update Pin
Tiny 20-Lead 4mm
×
4mm QFN and
16-Lead Narrow SSOP packages
APPLICATIONS
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Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
Automotive
BLOCK DIAGRAM
REFCOMP
GND
REFLO
REGISTER
REGISTER
REGISTER
REGISTER
V
OUTA
DAC A
DAC D
V
OUTD
INL (LSB)
INTERNAL REFERENCE
REFIN/OUT
INL Curve
V
CC
4
3
2
1
0
–1
DAC C
V
OUTC
–2
–3
POWER-ON
RESET
PORSEL
–4
128
16384
32768
CODE
49152
65535
2655 TA01b
V
CC
= 5V
REGISTER
REGISTER
REGISTER
V
OUTB
CA0
CA1
DAC B
32-BIT SHIFT REGISTER
CA2
SCL
LDAC
2-WIRE INTERFACE
REGISTER
SDA
2655 BD
2655f
1
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