TN5335
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
350V
*
Same as SOT-89.
R
DS(ON)
(max)
15Ω
V
GS(th)
(max)
2.0V
I
D(ON)
(min)
750mA
Order Number / Package
TO-236AB
TN5335K1
TO-243AA*
TN5335N8
Wafer
TN5335NW
Product supplied on 2000 piece carrier tape reels.
Features
❏
Low threshold – 2.0V max.
❏
High input impedance
❏
Low input capacitance
❏
Fast switching speeds
❏
Low on resistance
❏
Free from secondary breakdown
❏
Low input and output leakage
Product marking for SOT-23
Product marking for TO-243AA
N3S❋
Where
❋
= 2-week alpha date code
TN3S❋
Where
❋
= 2-week alpha date code
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex's well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Applications
❏
Logic level interfaces – ideal for TTL and CMOS
❏
Solid state relays
❏
Battery operated systems
❏
Photo voltaic drives
❏
Analog switches
❏
General purpose line drivers
❏
Telecom switches
❏
Modem hook switches
Package Options
D
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
11/12/01
D
G
G S
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
D
S
TO-236AB
(SOT-23)
top view
TO-243AA
(SOT-89)
Note: See Package Outline section for dimensions.
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
TN5335
Thermal Characteristics
Package
TO-236AB
TO-243AA
†
I
D
(continuous)*
110mA
230mA
I
D
(pulsed)
800mA
1.3A
Power Dissipation
@ T
A
= 25
°
C
0.36W
1.6W
†
θ
jc
°
C/W
200
15
θ
ja
°
C/W
350
78
†
I
DR
*
110mA
230mA
I
DRM
800mA
1.3A
*
I
D
(continuous) is limited by max rated T
j
.
Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P
D
increase possible on ceramic substrate.
Electrical Characteristics
(@ 25°C unless otherwise specified)
Symbol
BV
DSS
V
GS(th)
∆V
GS(th)
I
GSS
I
DSS
Parameter
Drain-to-Source Breakdown Voltage
Gate Threshold Voltage
Change in V
GS(th)
with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current
Min
350
0.6
Typ
Max
2.0
-4.5
100
1.0
10
1.0
5.0
I
D(ON)
R
DS(ON)
ON-State Drain Current
Static Drain-to Source
On-State Resistance
300
750
15
15
15
125
110
60
22
20
15
25
25
1.8
800
V
ns
V
GS
= 0V, I
SD
= 200mA
V
GS
= 0V, I
SD
= 200mA
ns
pF
V
GS
= 0V, V
DS
= 25V
f = 1Mhz
V
DD
= 25V,
I
D
= 150mA,
R
GEN
= 25Ω
1.0
Ω
%/°C
m
Unit
V
V
mV/°C
nA
µA
µA
mA
nA
mA
Conditions
V
GS
= 0V, I
D
= 100µA
V
GS
= V
DS
, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±
20V, V
DS
= 0V
V
GS
= 0V, V
DS
= 100V
V
GS
= 0V, V
DS
= Max Rating
V
GS
= 0V, V
DS
= 0.8 Max Rating
T
A
= 125°C
V
GS
= 0V, V
DS
= 330V
V
GS
= 4.5V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
V
GS
= 3.0V, I
D
= 20mA
V
GS
= 4.5V, I
D
= 150mA
V
GS
= 10V, I
D
= 200mA
V
GS
= 4.5V, I
D
= 150mA
V
DS
= 25V, I
D
= 200mA
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time
Notes:
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
90%
INPUT
0V
PULSE
GENERATOR
R
gen
10%
t
(ON)
t
(OFF)
t
r
t
d(OFF)
t
F
t
d(ON)
V
DD
10%
10%
INPUT
OUTPUT
0V
90%
90%
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
2
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
Ω
∆R
DS(ON)
G
FS
C
ISS
Change in R
DS(ON)
with Temperature
Forward Transconductance
Input Capacitance
V
DD
R
L
OUTPUT
D.U.T.
11/12/01
FPGA/CPLD
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