Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase These devices aid the system designer by combining the
functions of several components into one making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor
interface
The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of
8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment
conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s
MCS -186 family 80286 i386
TM
i486
TM
i860
TM
and 80960CA With exactly the same memory segmentation
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory
such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless
otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document
The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds low power consumption and immunity to noise Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown
mode lowers power consumption to 0 25
mW
typical through V
CC
crucial in laptop computer handheld instru-
mentation and other low-power applications The RP power control input also provides absolute data protec-
tion during system powerup or power loss
Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality reliability and cost-effectiveness
NOTE
The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290406-007
28F001BX-T 28F001BX-B
290406 –1
Figure 1 28F001BX Block Diagram
Table 1 Pin Description
Symbol
A
0
–A
16
DQ
0
–DQ
7
Type
INPUT
INPUT
OUTPUT
Name and Function
ADDRESS INPUTS
for memory addresses Addresses are internally latched during
a write cycle
DATA INPUTS OUTPUTS
Inputs data and commands during memory write
cycles outputs data during memory Status Register and Identifier read cycles The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled Data is internally latched during a write cycle
CHIP ENABLE
Activates the device’s control logic input buffers decoders and
sense amplifiers CE is active low CE high deselects the memory device and
reduces power consumption to standby levels
POWERDOWN
Puts the device in deep powerdown mode RP is active low
RP high gates normal operation RP
e
V
HH
allows programming of the boot
block RP also locks out erase or write operations when active low providing data
protection during power transitions RP active resets internal automation Exit
from deep powerdown sets device to Read Array mode
OUTPUT ENABLE
Gates the device’s outputs through the data buffers during a
read cycle OE is active low OE
e
V
HH
(pulsed) allows programming of the
boot block
WRITE ENABLE
Controls writes to the Command Register and array blocks WE
is active low Addresses and data are latched on the rising edge of the WE pulse
ERASE PROGRAM POWER SUPPLY
for erasing blocks of the array or
programming bytes of each block Note With V
PP
k
V
PPL
max memory contents
cannot be altered
DEVICE POWER SUPPLY
(5V
g
10%)
GROUND
CE
INPUT
RP
INPUT
OE
INPUT
WE
V
PP
INPUT
V
CC
GND
2
28F001BX-T 28F001BX-B
28F010
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
GND
290406 – 2
28F010
V
CC
WE
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
Figure 2 DIP Pin Configuration
28F010
A
11
A
9
A
8
A
13
A
14
NC
WE
V
CC
V
PP
A
16
A
15
A
12
A
7
A
6
A
5
A
4
28F010
OE
A
10
CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
GND
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
290406– 3
Figure 3 TSOP Lead Configuration
3
28F001BX-T 28F001BX-B
290406– 4
Figure 4 PLCC Lead Configuration
APPLICATIONS
The 28F001BX flash ‘boot block’ memory augments
the non-volatility in-system electrical erasure and
reprogrammability of Intel’s standard flash memory
by offering four separately erasable blocks and inte-
grating a state machine to control erase and pro-
gram functions The specialized blocking architec-
ture and automated programming of the 28F001BX
provide a full-function non-volatile flash memory
ideal for a wide range of applications including PC
boot BIOS memory minimum-chip embedded pro-
gram memory and parametric data storage The
28F001BX combines the safety of a hardware-pro-
tected 8-KByte boot block with the flexibility of three
separately reprogrammable blocks (two 4-KByte pa-
rameter blocks and one 112-KByte code block) into
one versatile cost-effective flash memory Addition-
ally reprogramming one block does not affect code
stored in another block ensuring data integrity
The flexibility of flash memory reduces costs
throughout the life cycle of a design During the early
stages of a system’s life flash memory reduces pro-
totype development and testing time allowing the
system designer to modify in-system software elec-
trically versus manual removal of components Dur-
ing production flash memory provides flexible firm-
ware for just-in-time configuration reducing system
inventory and eliminating unnecessary handling and
less reliable socketed connections Late in the life
cycle when software updates or code ‘‘bugs’’ are
often unpredictable and costly flash memory reduc-
es update costs by allowing the manufacturers to
send floppy updates versus a technician Alterna-
tively remote updates over a communication link are
possible at speeds up to 9600 baud due to flash
memory’s fast programming time
4
28F001BX-T 28F001BX-B
Reprogrammable environments such as the per-
sonal computer are ideal applications for the
28F001BX The internal state machine provides
SRAM-like timings for program and erasure using
the Command and Status Registers The blocking
scheme allows BIOS update in the main and param-
eter blocks while still providing recovery code in the
boot block in the unlikely event a power failure oc-
curs during an update or where BIOS code is cor-
rupted Parameter blocks also provide convenient
configuration storage backing up SRAM and battery
configurations EISA systems for example can
store hardware configurations in a flash parameter
block reducing system SRAM
Laptop BIOSs are becoming increasingly complex
with the addition of power management software
and extended system setup screens BIOS code
complexity increases the potential for code updates
after the sale but the compactness of laptop de-
signs makes hardware updates very costly Boot
block flash memory provides an inexpensive update
solution for laptops while reducing laptop obsoles-
cence For portable PCs and hand-held equipment
the deep powerdown mode dramatically lowers sys-
tem power requirements during periods of slow op-
eration or sleep modes
The 28F001BX gives the embedded system design-
er several desired features The internal state ma-
chine reduces the size of external code dedicated to
the erase and program algorithms as well as freeing
the microcontroller or microprocessor to respond to
other system requests during program and erasure
The four blocks allow logical segmentation of the
entire embedded software the 8-KByte block for the
boot code the 112-KByte block for the main pro-
gram code and the two 4-KByte blocks for updatable
parametric data storage diagnostic messages and
data or extensions of either the boot code or pro-
gram code The boot block is hardware protected
against unauthorized write or erase of its vital code
in the field Further the powerdown mode also locks
out erase or write operations providing absolute
data protection during system powerup or power
loss This hardware protection provides obvious ad-
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