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545AAA000278BAGR

Description
LVPECL Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size1MB,16 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

545AAA000278BAGR Overview

LVPECL Output Clock Oscillator,

545AAA000278BAGR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
JESD-609 codee4
Oscillator typeLVPECL
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
Ultra Series
Crystal Oscillator
Si545 Data Sheet
Ultra Low Jitter Any-Frequency XO (80 fs), 0.2 to 1500 MHz
The Si545 Ultra Series
oscillator utilizes Silicon Laboratories’ advanced 4
th
genera-
tion DSPLL
®
technology to provide an ultra-low jitter, low phase noise clock at any
output frequency. The device is factory-programmed to any frequency from 0.2 to
1500 MHz with <1 ppb resolution and maintains exceptionally low jitter for both inte-
ger and fractional frequencies across its operating range. The Si545 offers excellent
reliability and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection, simplify-
ing the task of generating low jitter clocks in noisy systems that use switched-mode
power supplies. Offered in industry-standard 3.2x5 mm and 5x7 mm footprints, the
Si545 has a dramatically simplified supply chain that enables Silicon Labs to ship cus-
tom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO,
where a different crystal is required for each output frequency, the Si545 uses one
simple crystal and a DSPLL IC-based approach to provide the desired output frequen-
cy. This process also guarantees 100% electrical testing of every device. The Si545 is
factory-configurable for a wide variety of user specifications, including frequency, out-
put format, and OE pin location/polarity. Specific configurations are factory-program-
med at time of shipment, eliminating the long lead times associated with custom oscil-
lators.
Pin Assignments
OE/NC
NC/OE
GND
VDD
CLK-
CLK+
KEY FEATURES
• Available with any frequency from 0.2
MHz to 1500 MHz
• Ultra low jitter: 80 fs Typ RMS
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise
immunity: –80 dBc Typ
• 7 ppm stability option (–40 to 85 °C)
• 3.3 V, 2.5 V and 1.8 V V
DD
supply
operation from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS,
and Dual CMOS output options
• 3.2×5, 5x7 mm package footprints
• Samples available with 1-2 week lead
times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast
video
• Datacenter
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
1
2
3
(Top View)
6
5
4
Pin #
1, 2
3
4
5
6
Descriptions
Selectable via ordering option
OE = Output enable; NC = No connect
GND = Ground
CLK+ = Clock output
NVM
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
OSC
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
Control
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
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