SI5338M-B10855-GM datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SI5338M-B10855-GM

SI5338M-B10855-GM: DescriptionProcessor Specific Clock Generator,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，46 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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SI5338M-B10855-GM Overview

Processor Specific Clock Generator,

SI5338M-B10855-GM Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	HVQCCN,
Reach Compliance Code	unknown
Other features	ALSO OPERATES WITH 2.5V NOM AND 3.3V NOMINAL
JESD-30 code	S-XQCC-N24
length	4 mm
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	200 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	710 MHz
Maximum seat height	0.9 mm
Maximum supply voltage	1.98 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Si5338

C - P

R O GRA MM A B LE

- F

R E Q U E N C Y

, A

- O

UTPUT

UAD

LOCK

ENERATOR

Features



Low power MultiSynth™ technology



enables independent, any-frequency

synthesis on four differential output



drivers

PCIe Gen 1/2/3/4 Common Clock and

Gen 3 SRNS compliant

Highly-configurable output drivers with



up to four differential outputs, eight

single-ended clock outputs, or a

combination of both



Low phase jitter of 0.7 ps RMS typ

High precision synthesis allows true

zero ppm frequency accuracy on all

outputs

Flexible input reference:



External

Single supply core with excellent

PSRR: 1.8, 2.5, 3.3 V

Independent frequency increment/

decrement feature enables

glitchless frequency adjustments in

1 ppm steps

Independent phase adjustment on

each of the output drivers with an

accuracy of <20 ps steps

Highly configurable spread

spectrum (SSC) on any output:

frequency from 5 to 350 MHz



Any spread from 0.5 to 5.0%



Any modulation rate from 33 to

63 kHz



Any

Ordering Information:

See page 42.

Pin Assignments

RSVD_GND

CLK0A

CLK0B

VDD

VDDO0



Independently configurable outputs

support any frequency or format:



LVPECL/LVDS:



HCSL:



0.16 to 710 MHz

0.16 to 250 MHz



CMOS: 0.16 to 200 MHz



SSTL/HSTL: 0.16 to 350 MHz



Independent output voltage per driver:

1.5, 1.8, 2.5, or 3.3 V

C/SMBus compatible interface

Easy to use programming software

Small size: 4 x 4 mm, 24-QFN

Low power: 45 mA core supply typ

Wide temperature range: –40 to

+85 °C

CLK1A

CLK1B

VDDO1

VDDO2

CLK2A

CLK2B

IN1

IN2

IN3

IN4

IN5

GND

Pad

Applications



IN6

Ethernet switch/router

PCIe Gen1/2/3/4

Broadcast video/audio timing

Processor and FPGA clocking



Any-frequency clock conversion

MSAN/DSLAM/PON

Fibre Channel, SAN

Telecom line cards

1 GbE and 10 GbE

INTR

Description

The Si5338 is a high-performance, low-jitter clock generator capable of

synthesizing any frequency on each of the device's four output drivers. This timing

IC is capable of replacing up to four different frequency crystal oscillators or

operating as a frequency translator. Using its patented MultiSynth™ technology,

the Si5338 allows generation of four independent clocks with 0 ppm precision.

Each output clock is independently configurable to support various signal formats

and supply voltages. The Si5338 provides low-jitter frequency synthesis in a

space-saving 4 x 4 mm QFN package. The device is programmable via an I

SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or

3.3 V core supply. I

C device programming is made easy with the ClockBuilder™

Desktop software available at

www.silabs.com/ClockBuilder.

Measuring PCIe

clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.

Download it for free at

www.silabs.com/pcie-learningcenter.

Rev. 1.6 12/15

VDDO3

VDD

CLK3B

CLK3A

SCL

SDA

crystal: 8 to 30 MHz



CMOS input: 5 to 200 MHz



SSTL/HSTL input: 5 to 350 MHz



Differential input: 5 to 710 MHz



External feedback mode allows

zero-delay mode



Loss of lock and loss of signal

alarms

Top View

Si5338

Si5338

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.9. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.10. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5. I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6. Si5338 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.1. Si5338 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Rev. 1.6

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