1825Y0100395JXT datasheet, PDF

1825Y0100395JXT: DescriptionCeramic Capacitor, Multilayer, Ceramic, 10V, X7R, -/+15ppm/Cel TC, 3.9uF, 1825; CategoryPassive components capacitor; File Size6MB，102 Pages; ManufacturerSyfer; Environmental Compliance

Download Datasheet Parametric View All

1825Y0100395JXT Overview

Ceramic Capacitor, Multilayer, Ceramic, 10V, X7R, -/+15ppm/Cel TC, 3.9uF, 1825

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Syfer
package instruction	, 1825
Reach Compliance Code	compliant
capacitance	3.9 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	2.5 mm
JESD-609 code	e3
length	6.3 mm
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	5%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	SMT
method of packing	TR, Embossed Plastic, 7 Inch
positive tolerance	5%
Rated (DC) voltage (URdc)	10 V
size code	1825
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
Terminal surface	Matte Tin (Sn) - with Nickel (Ni) barrier
Terminal shape	WRAPAROUND
width	4.5 mm

MLC

Capacitors

Let’s talk about gift giving during the Chinese New Year (and also talk about the E-coins on the forum): It's the end of the year again. I think I'm quite lucky. I've been on the forum for more than three years, and I seem to have won the annual award for three years, but the level is different. What sur...; 辛昕 Suggestions & Announcements

Simple fast short circuit protection circuit.jpg: [i=s] This post was last edited by paulhyde on 2014-9-15 09:38 [/i] Simple fast short circuit protection circuit...; zhshmzd123654 Electronics Design Contest

Ask, microcontroller interrupt: How do I set up a timer interrupt? How do I set up a random IO port as an interrupt pin?...; 不过机子 51mcu

How is I2>>IB derived in the DC path of the voltage divider bias circuit?: In the DC path of the voltage divider bias circuit, the book says that the current I2 on the bias resistor R2 is much larger than the base current IB, that is, I2>>IB. How is this derived?...; Erespreciosa Embedded System

Two problems encountered when running MIG layout and routing simulation: unable to call the signal line under the module and not recognizing the DDR behavior model: The background is to control the DDR SDRAM controller generated by MIG. The test environment is as follows: the top layer is TESTBENCH written by me, and there are two models under the top layer, one ...; zhj1985 FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components