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AS7C252MPFS18A-166TQCN

Description
2.5V 2M x 18 pipelined burst synchronous SRAM
Categorystorage    storage   
File Size494KB,18 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Environmental Compliance
Download Datasheet Parametric View All

AS7C252MPFS18A-166TQCN Overview

2.5V 2M x 18 pipelined burst synchronous SRAM

AS7C252MPFS18A-166TQCN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time3.5 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee3
length20 mm
memory density37748736 bi
Memory IC TypeSTANDARD SRAM
memory width18
Number of functions1
Number of terminals100
word count2097152 words
character code2000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2MX18
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)245
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
February 2005
®
AS7C252MPFD18A
2.5V 2M
×
18 pipelined burst synchronous SRAM
Features
Organization: 2,097,152 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.1/3.5/3.8 ns
Fast OE access time: 3.1/3.5/3.8 ns
Fully synchronous register-to-register operation
Double-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[20:0]
CLK
CS
CLR
Burst logic
Q
21
CS
Address
D
21
19 21
2M x 18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
CLK
D
registers
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.1
450
170
90
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
2/11/05, v.1.1
Alliance Semiconductor
1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
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