ISL6265C datasheet, PDF - EEWORLD Datasheet

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ISL6265C: DescriptionMulti-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs; File Size1MB，27 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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ISL6265C Overview

Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

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DATASHEET

ISL6265C

Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

Mobile CPUs

The ISL6265C is a multi-output controller with embedded gate

drivers. A single-phase controller powers the Northbridge

(VDDNB) portion of the CPU. The two remaining controller

channels can be configured for two-phase or individual

single-phase outputs. For uniplane CPU applications, the

ISL6265C is configured as a two-phase buck converter. This

allows the controller to interleave channels to effectively double

the output voltage ripple frequency, and thereby reduce output

voltage ripple amplitude with fewer components, lower

component cost, reduced power dissipation, and smaller area.

For dual-plane processors, the ISL6265C can be configured as

independent single-phase controllers powering VDD0 and

VDD1.

Technology™,

The heart of the ISL6265C is the patented

Intersil’s Robust Ripple Regulator modulator. Compared with

the traditional buck regulator, the R

Technology has a faster

transient response. This is due to the R

modulator

commanding variable switching frequency during a load

transient.

The Serial VID Interface (SVI) allows dynamic adjustment of

the Core and Northbridge output voltages independently and in

combination from 0.500V to 1.55V. Core and Northbridge

output voltages achieve a 0.5% system accuracy

over-temperature.

A unity-gain differential amplifier is provided for remote CPU

die sensing. This allows the voltage on the CPU die to be

accurately regulated per AMD mobile CPU specifications. Core

output current sensing is realized using lossless inductor DCR

sensing. All outputs feature overcurrent, overvoltage and

undervoltage protection.

FN6976

Rev 2.00

January 11, 2013

Features

• Core Configuration Flexibility

- Dual Plane, Single-Phase Controllers

- Uniplane, Two-Phase Controller

• Precision Voltage Regulators

- 0.5% System Accuracy Over-temperature

• Voltage Positioning with Adjustable Load Line and Offset

• Internal Gate Drivers with 2A Driving Capability

• Differential Remote CPU Die Voltage Sensing

• Core Differential Current Sensing: DCR or Resistor

• Northbridge Lossless r

DS(ON)

Current Sensing

• Serial VID Interface

- Two Wire Clock and Data Bus

- Supports High-Speed I

- 0.500V to 1.55V in 12.5mV Steps

- Supports PSI_L Power-Saving Mode

• Core Outputs Feature Phase Shedding with PSI_L

• Adjustable Output-Voltage Offset

• Digital Soft-Start of all Outputs

• User Programmable Switching Frequency

• Static and Dynamic Current Sharing (Uniplane Core)

• Overvoltage, Undervoltage, and Overcurrent Protection

• Pb-Free (RoHS compliant)

Related Literature

• See

FN6884

for “Multi-Output Controller with Integrated

MOSFET Drivers for AMD SVI Capable Mobile CPUs”

Applications

• AMD Griffin Platform CPU

• Notebook Core/GPU Voltage Regulators

CORE_0

ISL6265C

POWER

STAGE

CORE_1

POWER

STAGE

FIGURE 1. SIMPLIFIED SYSTEM DIAGRAM

FN6976 Rev 2.00

January 11, 2013

NORTHBRIDGE

POWER

STAGE

Page 1 of 27

ISL6265C

Pin Descriptions

PIN(s)

SYMBOL(s)

OFS/VFIXEN

DESCRIPTION

A resistor from this pin to GND programs a DC current source, which generates a positive offset voltage

across the resistor between FB and VDIFF pins. In this case, the OFS pin voltage is +1.2V and VFIX mode

is not enabled. If OFS is pulled up to +3.3V, VFIX mode is enabled, the DAC decodes the SVC and SVD

inputs to determine the programmed voltage, and the OFS function is disabled. If OFS is pulled up to +5V,

the OFS function and VFIX mode are disabled.

Controller power-good open-drain output. This pin is typically pulled up externally by a 2.0kΩ resistor to

+3.3V. During normal operation, this pin indicates whether all output voltages are within specified

overvoltage and undervoltage limits and no overcurrent condition is present. If any output voltage

exceeds these limits or a reset event occurs, the pin is pulled low. This pin is always low prior to the end

of soft-start.

System power good input. When this pin is high, the SVI interface is active and I

C protocol is running.

While this pin is low, the SVC, SVD, and VFIXEN input states determine the pre-PWROK metal VID or VFIX

mode voltage. This pin must be low prior to the ISL6265C PGOOD output going high per the AMD SVI

Controller Guidelines.

This pin is the serial VID data bidirectional signal to and from the master device on the AMD processor.

This pin is the serial VID clock input from the AMD processor.

Digital input enable. A high level logic signal on this pin enables the ISL6265C.

A 117kΩ resistor from RBIAS to GND sets internal reference currents. The addition of capacitance to this

pin must be avoided and can create instabilities in operation.

CORE_0 and CORE_1 common overcurrent protection selection input. The voltage on this pin sets the

(ISPx - ISNx) voltage limit for OC trip.

Output of the CORE_0 and CORE_1 differential amplifiers.

These pins are the output voltage feedback to the inverting input of the CORE_0 and CORE_1 error

amplifiers.

The output of the CORE_0 and CORE_1 controller error amplifiers respectively. FBx, VDIFFx, and COMPx

pins are tied together through external R-C networks to compensate the regulator

A resistor from this pin to corresponding COMPx pin programs the switching frequency (for example,

6.81k ~ 300kHz).

These pins are used for differentially sensing the corresponding channel output current. The sensed

current is used for channel balancing, protection, and core load line regulation.

Connect ISN0 and ISN1 to the node between the RC sense elements surrounding the inductor of their

respective channel. Tie the ISP0 and ISP1 pins to the VCORE side of their corresponding channel’s sense

capacitor. These pins can also be used for discrete resistor sensing.

Inputs to the CORE_0 VR controller precision differential remote sense amplifier. Connect to the sense

pins of the VDD0_FB[H,L] portion of the processor.

Inputs to the CORE_1 VR controller precision differential remote sense amplifier. Connect to the sense

pins of the VDD1_FB[H,L] portion of the processor. The RTN1 pin is also used for detection of the

VDD_PLANE_STRAP signal prior to enable.

The power supply pin for the internal MOSFET gate drivers of the ISL6265C. Connect this pin to a +5V

power supply. Decouple this pin with a quality 1.0µF ceramic capacitor.

Connect these pins to the corresponding lower MOSFET gate(s).

The return path of the lower gate driver for CORE_0 and CORE_1 respectively. Connect these pins to the

corresponding sources of the lower MOSFETs.

Switch node of the CORE_0 and CORE_1 controllers. Connect these pins to the sources of the

corresponding upper MOSFET(s). These pins are the return path for the upper MOSFET drives.

Connect these pins to the corresponding upper MOSFET gate(s). These pins control the upper MOSFET

gate(s) and are monitored for shoot-through prevention.

These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to

appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin

provide the necessary bootstrap charge.

PGOOD

PWROK

9, 19

10, 20

11, 21

12, 22

13, 14, 23, 24

SVD

SVC

ENABLE

RBIAS

OCSET

VDIFF0, VDIFF1

FB0, FB1

COMP0, COMP1

VW0, VW1

ISP0, ISN0, ISP1, ISN1

15, 16

18, 17

VSEN0, RTN0

VSEN1, RTN1

31, 29

32, 28

33, 27

34, 26

35, 25

PVCC

LGATE0, LGATE1

PGND0, PGND1

PHASE0, PHASE1

UGATE0, UGATE1

BOOT0, BOOT1

FN6976 Rev 2.00

January 11, 2013

Page 4 of 27

ISL6265C Related Products

	ISL6265C	ISL6265C_10
Description	Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs	Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

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