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AS7C25512NTD36A-166TQC

Description
2.5V 512K x 32/36 Pipelined SRAM with NTD
Categorystorage    storage   
File Size409KB,18 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C25512NTD36A-166TQC Overview

2.5V 512K x 32/36 Pipelined SRAM with NTD

AS7C25512NTD36A-166TQC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time3.5 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density18874368 bi
Memory IC TypeZBT SRAM
memory width36
Number of functions1
Number of terminals100
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.04 A
Minimum standby current2.38 V
Maximum slew rate0.29 mA
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
December 2004
®
AS7C25512NTD32A
AS7C25512NTD36A
2.5V 512K × 32/36 Pipelined SRAM with NTD
TM
Features
Organization: 524,288 words × 32 or 36 bits
NTD
architecture for efficient bus operation
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/3.8 ns
Fast OE access time: 3.5/3.8 ns
Fully synchronous operation
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Clock enable for operation hold
Multiple chip enables for easy expansion
2.5V core power supply
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[18:0]
19
D
Address
register
Burst logic
Q
19
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
19
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
512K x 32/36
SRAM
Array
DQ[a,b,c,d]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ[a,b,c,d]
Selection guide
-166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
290
85
40
-133
7.5
133
3.8
270
75
40
Units
ns
MHz
ns
mA
mA
mA
12/23/04, v 2.2
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
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