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AS7C31025B-20JC

Description
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Categorystorage    storage   
File Size90KB,9 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C31025B-20JC Overview

3.3V 128K X 8 CMOS SRAM (Center power and ground)

AS7C31025B-20JC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeSOJ
package instruction0.400 INCH, SOJ-32
Contacts32
Reach Compliance Codeunknow
ECCN code3A991.B.2.B
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee0
length20.955 mm
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.44
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum seat height3.7084 mm
Maximum standby current0.005 A
Minimum standby current3 V
Maximum slew rate0.055 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
March 2004
®
AS7C31025B
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
• Low power consumption: STANDBY
- 18 mW / max CMOS
• 6 T 0.18 u CMOS technology
Easy memory expansion with CE, OE inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• ESD protection
2000 volts
• Latch-up current
200 mA
Pin arrangement
Logic block diagram
V
CC
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O7
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
Row decoder
512 x 256 x 8
Array
(1,048,576)
I/O0
WE
OE
CE
Column decoder
A9
A10
A11
A12
A13
A14
A15
A16
Control
circuit
Selection guide
-10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
10
5
70
5
-12
12
6
65
5
-15
15
7
60
5
-20
20
8
55
5
Unit
ns
ns
mA
mA
3/24/04, v. 1.3
Alliance Semiconductor
AS7C31025B
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