High Performance
32K
×
8
CMOS SRAM
32K
×
8 CMOS SRAM (Common I/O)
FEATURES
• Organization: 32,768 words
×
8 bits
• High speed
– 10/12/15/20/25/35 ns address access time
– 3/3/4/5/6/8 ns output enable access time
• Low power consumption
– Active:
– Standby:
660 mW max (10 ns cycle)
11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
• Equal access and cycle times
AS7C256
AS7C256L
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
– 300 mil PDIP and SOJ
Socket compatible with 7C512 and 7C1024
– 330 mil SOIC
– 8×13.4 TSOP
• ESD protection > 2000 volts
• Latch-up current > 200 mA
– Very low DC component in active power
• 2.0V data retention (L version)
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
DIP, SOJ, SOIC
Vcc
GND
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A14
ROW DECODER
I/O7
256×128×8
ARRAY
(262,144)
SENSE AMP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
COLUMN DECODER
WE
CONTROL
CIRCUIT
OE
CE
TSOP 8
×
13.4
A A A A A A A
7 8 9 10 11 12 13
AS7C256-01
SELECTION GUIDE
7C256-10
Maximum Address Access Time
Maximum Output Enable Access Time
Maximum Operating Current
Maximum CMOS Standby Current
10
3
120
2.0
L
0.5
7C256-12
12
3
115
2.0
0.5
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
AS7C256
AS7C256
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
AS7C256-02
A1
A2
7C256-15
15
4
110
2.0
0.5
7C256-20
20
5
100
2.0
0.5
7C256-25
25
6
90
2.0
0.5
7C256-35
35
8
80
2.0
0.5
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
AS7C256
AS7C256L
FUNCTIONAL DESCRIPTION
The AS7C256 is a high performance CMOS 262,144-bit
Static Random Access Memory (SRAM) organized as
32,768 words
×
8 bits. It is designed for memory applica-
tions where fast data access, low power, and simple interfac-
ing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of
10/12/15/20/25/35 ns with output enable access times (t
OE
)
of 3/3/4/5/6/8 ns are ideal for high performance applica-
tions. A chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.
When CE is HIGH the device enters standby mode. The
standard AS7C256 is guaranteed not to exceed 11 mW
power consumption in standby mode; the L version is guar-
anteed not to exceed 2.75 mW, and typically requires only
500
µW.
The L version also offers 2.0V data retention, with
maximum power consumption in this mode of 300
µW.
A write cycle is accomplished by asserting chip enable (CE)
and write enable (WE) LOW. Data on the input pins
I/O0-I/O7 is written on the rising edge of WE (write cycle 1)
or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE)
and output enable (OE) LOW, with write enable (WE)
HIGH. The chip drives I/O pins with the data word refer-
enced by the input address. When chip enable or output
enable is HIGH, or write enable is LOW, output drivers stay
in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and opera-
tion is from a single 5V supply. The AS7C256 is packaged
in all high volume industry standard packages.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to GND
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
DC Output Current
Symbol
V
t
P
D
T
stg
T
bias
I
out
Min
–0.5
–
–55
–10
–
Max
+7.0
1.0
+150
+85
20
Unit
V
W
o
C
o
C
mA
NOTE:
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
.
TRUTH TABLE
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
out
D
in
Mode
Standby (I
SB
, I
SB1
)
Output Disable
Read
Write
Key:
X = Don’t Care, L = LOW, H = HIGH
2
AS7C256
AS7C256L
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
V
CC
GND
V
IH
V
IL
Min
4.5
0.0
2.2
–0.5*
Typ
5.0
0.0
–
–
(T
a
= 0°C to +70°C)
Max
5.5
0.0
V
CC
+1
0.8
Unit
V
V
V
V
Input Voltage
*V
IL
min = –3.0V for pulse width less than t
RC
/2.
DC OPERATING CHARACTERISTICS
1
-10
Parameter
Input Leakage
Current
Output Leakage
Current
Operating Power
Supply Current
Symbol Test Conditions
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-12
-15
-20
-25
-35
Min Max Min Max Min Max Min Max Min Max Min Max Unit
–
–
–
L
–
–
L
–
–
L
–
–
2.4
1
1
120
115
45
40
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
–
2.4
1
1
115
110
40
35
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
–
2.4
1
1
110
105
30
25
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
–
2.4
1
1
100
95
30
25
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
–
2.4
1
1
90
85
25
20
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
–
2.4
1
1
80
75
25
20
2.0
0.5
0.4
–
|
I
LI
|
|
I
LO
|
I
CC
I
SB
V
CC
= Max,
V
in
= GND to V
CC
CE = V
IH
, V
CC
= Max,
V
out
= GND to V
CC
CE = V
IL
,
f
=
f
max,
I
out
= 0 mA
CE = V
IH
,
f
=
f
max
CE > V
CC
–0.2V,
f
= 0,
V
in
≤
0.2V
or
V
in
≥
V
CC
–0.2V
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
µ
A
µ
A
mA
mA
mA
mA
mA
mA
V
V
Standby
Power Supply
Current
I
SB1
V
OL
V
OH
Output Voltage
CAPACITANCE
2
Parameter
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE
I/O
(f = 1 MHz, T
a
= Room Temperature, V
CC
= 5V)
Test Conditions
V
in
= 0V
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
3
AS7C256
AS7C256L
READ CYCLE
3, 9
-10
Parameter
Read Cycle Time
Address Access Time
Chip Enable (CE) Access Time
Output Enable (OE) Access Time
Output Hold from Address Change
CE LOW to Output in Low Z
CE HIGH to Output in High Z
OE LOW to Output in Low Z
OE HIGH to Output in High Z
Power Up Time
Power Down Time
-12
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-15
-20
-25
-35
Notes
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
10
–
–
–
2
3
–
0
–
0
–
–
10
10
3
–
–
3
–
3
–
10
12
–
–
–
3
3
–
0
–
0
–
–
12
12
3
–
–
3
–
3
–
12
15
–
–
–
3
3
–
0
–
0
–
–
15
15
4
–
–
4
–
4
–
15
20
–
–
–
3
3
–
0
–
0
–
–
20
20
5
–
–
5
–
5
–
20
25
–
–
–
3
3
–
0
–
0
–
–
25
25
6
–
–
6
–
6
–
25
35
–
–
–
3
3
–
0
–
0
–
–
35
35
8
–
–
8
–
8
–
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
TIMING WAVEFORM OF READ CYCLE 1
3, 6, 7, 9
t
RC
Address
t
AA
D
out
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
(Address Controlled)
t
OH
Data Valid
TIMING WAVEFORM OF READ CYCLE 2
3, 6, 8, 9
t
RC1
CE
AAAAAAAAAAAAAAAAAAAAAAAAA
OE
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
(CE Controlled)
t
OE
t
OLZ
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t
ACE
D
out
t
CLZ
Supply
Current
t
PU
t
OHZ
t
CHZ
Data Valid
t
PD
I
CC
I
SB
AS7C256-04
50%
50%
4
AS7C256
AS7C256L
WRITE CYCLE
11
-10
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Address Hold From End of Write
Data Valid to Write End
Data Hold Time
Write Enable to Output in High Z
Output Active from Write End
-12
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-15
-20
-25
-35
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
10
9
9
0
7
0
6
0
–
3
–
–
–
–
–
–
–
–
5
–
12
10
10
0
8
0
6
0
–
3
–
–
–
–
–
–
–
–
5
–
15
12
12
0
9
0
8
0
–
3
–
–
–
–
–
–
–
–
5
–
20
12
12
0
12
0
10
0
–
3
–
–
–
–
–
–
–
–
5
–
20
15
15
0
15
0
10
0
–
3
–
–
–
–
–
–
–
–
5
–
30
20
20
0
17
0
15
0
–
3
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
TIMING WAVEFORM OF WRITE CYCLE 1
10, 11
t
WC
t
AW
Address
WE
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
(WE Controlled)
t
AH
t
WP
t
DW
Data Valid
t
WZ
t
OW
t
DH
t
AS
D
in
D
out
AS7C256-05
TIMING WAVEFORM OF WRITE CYCLE 2
10, 11
t
WC
t
AW
Address
t
AS
CE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
(CE Controlled)
t
AH
t
CW
t
WP
t
WZ
t
DW
Data Valid
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AS7C256-06
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t
DH
D
in
D
out
5
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