regulator. It features 45µA quiescent current, dropping
to 10µA in shutdown. A new reference amplifier topology
gives precision DC characteristics along with the ability to
maintain good loop stability with an extremely wide range
of output capacitors. Very low dropout voltage and high
efficiency are obtained with a unique power transistor
anti-saturation design. Adjustable and fixed 5V versions
are available.
Several new features make the LT1175 very user-friendly.
The SHDN pin can interface directly to either positive or
negative logic levels. Current limit is user-selectable at
200mA, 400mA, 600mA and 800mA. The output can be
forced to reverse voltage without damage or latchup. Un-
like some earlier designs, the increase in quiescent current
during a dropout condition is actively limited.
The LT1175 has complete blowout protection with current
limiting, power limiting and thermal shutdown. Special
attention was given to the problem of high temperature
operation with micropower operating currents, preventing
output voltage rise under no-load conditions. The LT1175
is available in 8-pin PDIP and SO packages, 3-lead SOT-
223 as well as 5-pin surface mount DD and through-hole
TO-220 packages. The 8-pin SO package is specially
constructed for low thermal resistance.
Minimum Input-to-Output Voltage
1.0
INPUT-TO-OUTPUT VOLTAGE (V)
T
J
= 25°C
I
LIM2
, I
LIM4
TIED TO V
IN
Operating Current: 45µA
Adjustable Current Limit
Low Voltage Linear Dropout Characteristics
Stable with Wide Range of Output Capacitors
Shutdown Current: 10µA
Positive or Negative Shutdown Logic
Fixed 5V and Adjustable Versions
Tolerates Reverse Output Voltage
Available in 8-pin PDIP and SO Packages, 3-lead
SOT-223, 5-Pin Surface Mount DD and Through-Hole
TO-220 Packages
applicaTions
n
n
n
n
n
n
Analog Systems
Modems
Instrumentation
A/D and D/A Converters
Interface Drivers
Battery-Powered Systems
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
Typical LT1175 Connection
+
SHDN
V
IN
I
LIM2
I
LIM4
LT1175-5
OUTPUT
GND
SENSE
0.8
C
IN
*
–V
IN
+
C
OUT
≥ 0.1µF
–5V
UP TO 500mA
0.6
0.4
0.2
*C
IN
IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM
INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION
1175 TA01
SECTION FOR DETAILS
0
0
0.1
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
0.6
0.7
1175 TA02
1175fe
LT1175
absoluTe MaxiMuM raTings
(Note 1)
Input Voltage (Transient 1 sec, Note 11) ...................25V
Input Voltage (Continuous) .......................................20V
Input-to-Output Differential Voltage (Note 12) ..........20V
5V SENSE Pin (with Respect to GND Pin) ......... 2V, –10V
ADJ SENSE Pin
(with Respect to OUTPUT Pin)...................20V, –0.5V
5V SENSE Pin
(with Respect to OUTPUT Pin)......................20V, –7V
Output Reverse Voltage ..............................................2V
SHDN
Pin to GND Pin Voltage (Note 2) ........ 13.5V, –20V
SHDN
Pin to V
IN
Pin Voltage .............................30V, –5V
Operating Junction Temperature Range
LT1175C ................................................. 0°C to 125°C
LT1175I .............................................. –40°C to 125°C
Ambient Operating Temperature Range
LT1175C ................................................... 0°C to 70°C
LT1175I ................................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
pin conFiguraTion
TOP VIEW
V
IN
1
I
LIM2
2
OUTPUT 3
SENSE 4
8
7
6
5
V
IN
I
LIM4
SHDN
GND
TAB
IS
V
IN
FRONT VIEW
5
4
3
2
1
SHDN
GND
V
IN
SENSE
OUTPUT
TAB IS
V
IN
FRONT VIEW
3
2
1
GND
V
IN
OUTPUT
N8 PACKAGE
8-LEAD PDIP
θ
JA
= 80°C/W TO 120°C/W
DEPENDING ON PC BOARD LAYOUT
TOP VIEW
V
IN
1
I
LIM2
2
OUTPUT 3
SENSE 4
8
7
6
5
V
IN
I
LIM4
SHDN
GND
Q PACKAGE
5-LEAD PLASTIC DD
θ
JA
= 27°C/W TO 60°C/W
DEPENDING ON PC MOUNTING.
SEE DATA SHEET FOR DETAILS
ST PACKAGE
3-LEAD PLASTIC SOT-223
θ
JA
= 50°C/W
WITH BACKPLANE AND 10cm
2
TOPSIDE LAND SOLDERED TO TAB
FRONT VIEW
5
4
3
2
1
TAB IS
V
IN
T PACKAGE
5-LEAD PLASTIC TO-220
θ
JA
= 50°C/W,
θ
JC
= 5°C/W
SHDN
GND
V
IN
SENSE
OUTPUT
S8 PACKAGE
8-LEAD PLASTIC SO
θ
JA
= 60°C/W TO 100°C/W
DEPENDING ON PC BOARD LAYOUT
PINS 1, 8 ARE INTERNALLY CONNECTED TO DIE ATTACH PADDLE FOR HEAT SINKING.
ELECTRICAL CONTACT CAN BE MADE TO EITHER PIN. FOR BEST THERMAL RESISTANCE,
PINS 1, 8 SHOULD BE CONNECTED TO AN EXPANDED LAND THAT IS OVER AN INTERNAL
OR BACKSIDE PLANE.
SEE APPLICATIONS INFORMATION
1175fe
LT1175
orDer inForMaTion
LEAD FREE FINISH
LT1175CN8#PBF
LT1175CN8-5#PBF
LT1175CS8#PBF
LT1175CS8-5#PBF
LT1175CST-5#PBF
LT1175CQ#PBF
LT1175CQ-5#PBF
LT1175CT#PBF
LT1175CT-5#PBF
LT1175IN8#PBF
LT1175IN8-5#PBF
LT1175IS8#PBF
LT1175IS8-5#PBF
LT1175IST-5#PBF
LT1175IQ#PBF
LT1175IQ-5#PBF
LT1175IT#PBF
LT1175IT-5#PBF
LEAD BASED FINISH
LT1175CN8
LT1175CN8-5
LT1175CS8
LT1175CS8-5
LT1175CST-5
LT1175CQ
LT1175CQ-5
LT1175CT
LT1175CT-5
LT1175IN8
LT1175IN8-5
LT1175IS8
LT1175IS8-5
LT1175IST-5
LT1175IQ
LT1175IQ-5
LT1175IT
LT1175IT-5
TAPE AND REEL
LT1175CN8#TRPBF
LT1175CN8-5#TRPBF
LT1175CS8#TRPBF
LT1175CS8-5#TRPBF
LT1175CST-5#TRPBF
LT1175CQ#TRPBF
LT1175CQ-5#TRPBF
LT1175CT#TRPBF
LT1175CT-5#TRPBF
LT1175IN8#TRPBF
LT1175IN8-5#TRPBF
LT1175IS8#TRPBF
LT1175IS8-5#TRPBF
LT1175IST-5#TRPBF
LT1175IQ#TRPBF
LT1175IQ-5#TRPBF
LT1175IT#TRPBF
LT1175IT-5#TRPBF
TAPE AND REEL
LT1175CN8#TR
LT1175CN8-5#TR
LT1175CS8#TR
LT1175CS8-5#TR
LT1175CST-5#TR
LT1175CQ#TR
LT1175CQ-5#TR
LT1175CT#TR
LT1175CT-5#TR
LT1175IN8#TR
LT1175IN8-5#TR
LT1175IS8#TR
LT1175IS8-5#TR
LT1175IST-5#TR
LT1175IQ#TR
LT1175IQ-5#TR
LT1175IT#TR
LT1175IT-5#TR
PART MARKING*
LT1175CN8
LT1175CN8-5
1175
11755
11755
LT1175CQ
LT1175CQ-5
LT1175CT
LT1175CT-5
LT1175IN8
LT1175IN8-5
1175I
1175I5
1175I5
LT1175IQ
LT1175IQ-5
LT1175IT
LT1175IT-5
PART MARKING*
LT1175CN8
LT1175CN8-5
1175
11755
11755
LT1175CQ
LT1175CQ-5
LT1175CT
LT1175CT-5
LT1175IN8
LT1175IN8-5
1175I
1175I5
1175I5
LT1175IQ
LT1175IQ-5
LT1175IT
LT1175IT-5
PACKAGE DESCRIPTION
8-Lead Plastic Dip
8-Lead Plastic Dip
8-Lead Plastic SO
8-Lead Plastic SO
3-Lead Plastic SOT-223
5-Lead Plastic DD-Pak
5-Lead Plastic DD-Pak
5-Lead Plastic TO-220
5-Lead Plastic TO-220
8-Lead Plastic Dip
8-Lead Plastic Dip
8-Lead Plastic SO
8-Lead Plastic SO
3-Lead Plastic SOT-223
5-Lead Plastic DD-Pak
5-Lead Plastic DD-Pak
5-Lead Plastic TO-220
5-Lead Plastic TO-220
PACKAGE DESCRIPTION
8-Lead Plastic Dip
8-Lead Plastic Dip
8-Lead Plastic SO
8-Lead Plastic SO
3-Lead Plastic SOT-223
5-Lead Plastic DD-Pak
5-Lead Plastic DD-Pak
5-Lead Plastic TO-220
5-Lead Plastic TO-220
8-Lead Plastic Dip
8-Lead Plastic Dip
8-Lead Plastic SO
8-Lead Plastic SO
3-Lead Plastic SOT-223
5-Lead Plastic DD-Pak
5-Lead Plastic DD-Pak
5-Lead Plastic TO-220
5-Lead Plastic TO-220
TEMPERATURE RANGE
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
1175fe
LT1175
elecTrical characTerisTics
PARAMETER
Feedback Sense Voltage
Output Voltage Initial Accuracy
Output Voltage Accuracy (All Conditions)
Quiescent Input Supply Current
GND Pin Current Increase with Load (Note 4)
Input Supply Current in Shutdown
Shutdown Thresholds (Note 9)
SHDN
Pin Current (Note 2)
Output Bleed Current in Shutdown (Note 6)
SENSE Pin Input Current
Dropout Voltage (Note 7)
V
SHDN
= 0V
l
The
l
denotes specifications which apply over the operating temperature
range, otherwise specifications are at T
A
= 25°C. V
OUT
= 5V, V
IN
= 7V, I
OUT
= 0, V
SHDN
= 3V, I
LIM2
and I
LIM4
tied to V
IN
, T
J
= 25°C, unless
otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values
except where polarity is not obvious.
CONDITIONS
Adjustable Part
Fixed 5V Part
Adjustable, Measured at 3.8V Sense
Fixed 5V
V
IN
– V
OUT
= 1V to V
IN
= 20V, I
OUT
= 0A to 500mA
P = 0 to P
MAX
, T
J
= T
MIN
to T
MAX
(Note 3)
V
IN
– V
OUT
≤ 12V
l
l
l
MIN
3.743
4.93
TYP
3.8
5.0
0.5
0.5
1.5
45
10
10
MAX
3.857
5.075
1.5
1.5
2.5
65
80
20
20
25
2.5
8
4
1
5
150
20
0.2
0.26
0.7
0.5
0.45
0.45
1300
975
650
325
0.015
0.35
0.1
0.2
1.25
UNITS
V
V
%
%
%
µA
µA
µA/mA
µA
µA
V
µA
µA
µA
µA
nA
µA
V
V
V
V
V
V
mA
mA
mA
mA
%/V
%
%/W
%/W
%
Either Polarity On
SHDN
Pin
V
SHDN
= 0V to 10V (Flows Into Pin)
V
SHDN
= –15V to 0V (Flows Into Pin)
V
OUT
= 0V, V
IN
= 15V
l
l
0.8
4
1
0.1
1
75
12
0.1
0.18
0.5
0.33
0.3
0.26
520
390
260
130
800
600
400
200
0.003
0.1
0.04
0.1
0.25
l
(Adjustable Part Only, Current Flows Out of Pin)
(Fixed Voltage Only, Current Flows Out of Pin)
I
OUT
= 25mA
I
OUT
= 100mA
I
OUT
= 500mA
I
LIM2
Open, I
OUT
= 300mA
I
LIM4
Open, I
OUT
= 200mA
I
LIM2
, I
LIM4
Open, I
OUT
= 100mA
V
IN
– V
OUT
= 1V to 12V
I
LIM2
Open
I
LIM4
Open
I
LIM2
, I
LIM4
Open
V
IN
– V
OUT
= 1V to V
IN
= 20V
I
OUT
= 0mA to 500mA
P = 0 to P
MAX
(Notes 3, 8)
T
J
= 25°C to T
JMIN
, or 25°C to T
JMAX
5-Pin Packages
8-Pin Packages
l
l
l
l
l
l
l
l
l
l
l
l
l
l
Current Limit (Note 11)
Line Regulation (Note 10)
Load Regulation (Note 5, 10)
Thermal Regulation
Output Voltage Temperature Drift
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
SHDN
pin maximum positive voltage is 30V with respect to
– V
IN
and 13.5V with respect to GND. Maximum negative voltage is –20V
with respect to GND and –5V with respect to –V
IN
.
Note 3:
P
MAX
= 1.5W for 8-pin packages, and 6W for 5-pin packages.
This power level holds only for input-to-output voltages up to 12V, beyond
which internal power limiting may reduce power. See Guaranteed Current
Limit curve in Typical Performance Characteristics section. Note that all
conditions must be met.
Note 4:
GND pin current increases because of power transistor base
drive. At low input-to-output voltages (<1V) where the power transistor
is in saturation, GND pin current will be slightly higher. See Typical
Performance Characteristics.
Note 5:
With I
LOAD
= 0, at T
J
> 125°C, power transistor leakage could
increase higher than the 10µA to 25µA drawn by the output divider or fixed
voltage SENSE pin, causing the output to rise above the regulated value.
To prevent this condition, an internal active pull-up will automatically turn
on, but supply current will increase.
Note 6:
This is the current required to pull the output voltage to within 1V
of ground during shutdown.
Note 7:
Dropout voltage is measured by setting the input voltage equal to
the normal regulated output voltage and measuring the difference between
V
IN
and V
OUT
. For currents between 100mA and 500mA, with both I
LIM
pins tied to V
IN
, maximum dropout can be calculated from
V
DO
= 0.15 + 1.1Ω (I
OUT
).
1175fe
LT1175
elecTrical characTerisTics
Note 8:
Thermal regulation is a change in the output voltage caused by
die temperature gradients, so it is proportional to chip power dissipation.
Temperature gradients reach final value in less than 100ms. Output voltage
changes after 100ms are due to absolute die temperature changes and
reference voltage temperature coefficient.
Note 9:
The lower limit of 0.8V is guaranteed to keep the regulator in
shutdown. The upper limit of 2.5V is guaranteed to keep the regulator
active. Either polarity may be used, referenced to GND pin.
Note 10:
Load and line regulation are measured on a pulse basis with
pulse width of 20ms or less to keep chip temperature constant. DC
regulation will be affected by thermal regulation (Note 8) and chip
temperature changes. Load regulation specification also holds for currents
up to the specified current limit when I
LIM2
or I
LIM4
are left open.
Note 11:
Current limit is reduced for input-to-output voltage above 12V.
See the graph in Typical Performance Characteristics for guaranteed limits
above 12V.
Note 12:
Operating at very large input-to-output differential voltages
(>15V) with load currents less than 5mA requires an output capacitor with
an ESR greater than 1Ω to prevent low level output oscillations.
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FPGA/CPLD
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