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AS7C33128FT36B-10TQCN

Description
3.3V 128K x 32/36 Flow Through Synchronous SRAM
Categorystorage    storage   
File Size407KB,19 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Environmental Compliance
Download Datasheet Parametric View All

AS7C33128FT36B-10TQCN Overview

3.3V 128K x 32/36 Flow Through Synchronous SRAM

AS7C33128FT36B-10TQCN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time10 ns
Other featuresFLOW-THROUGH ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee3
length20 mm
memory density4718592 bi
Memory IC TypeSTANDARD SRAM
memory width36
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX36
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)245
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
February 2005
®
AS7C33128FT32B
AS7C33128FT36B
3.3V 128K
×
32/36 Flow Through Synchronous SRAM
Features
Organization: 131,072 words × 32 or 36 bits
Fast clock to data access: 6.5/7.5/8.0/10.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow through operation
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and Global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Snooze mode for reduced power standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
19
Q0
Burst logic
Q1
19
D
Q
CE
Address
register
CLK
D
DQ
d
Q
Byte write
registers
CLK
D
DQ
Q
c
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
36/32
DQ[a:d]
Q
D
BW
a
CE0
CE1
CE2
4
CLK
CE
CLR
17
19
128K × 32/36
Memory
array
GWE
BWE
BW
d
36/32
36/32
BW
c
BW
b
OE
Output
buffer
Input
registers
CLK
ZZ
OE
Selection guide
–65
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
7.5
6.5
275
90
30
-75
8.5
7.5
250
85
30
-80
10
8.0
215
75
30
-10
12
10.0
185
75
30
Units
ns
ns
mA
mA
mA
2/8/05; v.1.2
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
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