April 2005
®
AS7C33128NTD18B
3.3V 128K×18 Pipelined SRAM with NTD
TM
Features
• Organization: 131,072 words × 18 bits
• NTD
™
architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
Logic block diagram
A[16:0]
17
D
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Address
register
Burst logic
Q
17
17
Write delay
addr. registers
CLK
D
Q
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
DQ [a:b]
18
17
Control
logic
CLK
CLK
Write Buffer
128K x 18
SRAM
Array
D
Data
Q
Input
Register
CLK
18
18
18
18
CLK
CEN
CLK
OE
Output
Register
18
OE
DQ [a:b]
Selection Guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
135
30
-166
6
166
3.5
350
120
-133
7.5
133
4
325
110
Units
ns
MHz
ns
mA
mA
mA
30
30
4/28/05;
v.1.3
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128NTD18B
®
2 Mb Synchronous SRAM products list
1,2
Org
128KX18
64KX32
64KX36
128KX18
64KX32
64KX36
128KX18
64KX32
64KX36
128KX18
64KX32
64KX36
128KX18
64KX32
64KX36
Part Number
AS7C33128PFS18B
AS7C3364PFS32B
AS7C3364PFS36B
AS7C33128PFD18B
AS7C3364PFD32B
AS7C3364PFD36B
AS7C33128FT18B
AS7C3364FT32B
AS7C3364FT36B
AS7C33128NTD18B
AS7C3364NTD32B
AS7C3364NTD36B
AS7C33128NTF18B
AS7C3364NTF32B
AS7C3364NTF36B
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed3
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
7.5/8.0/10 ns
7.5/8.0/10 ns
7.5/8.0/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability.
PL-SCD
PL-DCD
FT
NTD
1
-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTD
TM
Flow-through Burst Synchronous SRAM with NTD
TM
1NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
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Alliance Semiconductor
P. 2 of 19
AS7C33128NTD18B
®
Pin arrangement for TQFP (top view)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
NC
A
A
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
NC
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14x20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQPa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
V
SS
NC
V
DD
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
4/28/05;
v.1.3
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
NC
Alliance Semiconductor
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32
33
34
35
36
37
38
39
40
41
42
43
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AS7C33128NTD18B
®
Functional description
The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM)
organized as 131,072 words × 18 bits and incorporates a LATE LATE Write.
This variation of the 2Mb sychronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced
Write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a Read command follows this Write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or Read-Modify-Write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle
pipeline (flowthrough) read latency. Write data is applied two cycles after the Write command and address, allowing the Read
pipeline to clear. With NTD
™
, Write and Read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform Write cycles. Byte Write enable controls write access to specific bytes, or can be tied low for full
18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is
applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled
for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-
selected by any of the three chip enable inputs (refer to Synchronous truth table on page 6). In pipeline mode, a two cycle
deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1 the clock enable input.
The AS7C33128NTD18B operates with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate
power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP
package.
TQFP Capacitance
Parameter
Input capacitance
I/O capacitance
*Guranteed not tested
Symbol
C
IN*
C
I/O*
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
1–layer
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
4/28/05;
v.1.3
Alliance Semiconductor
P. 4 of 19
AS7C33128NTD18B
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b]
OE
LBO
ZZ
NC
I/O Properties Description
I
I
I
I/O
I
I
I
I
I
I
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is HIGH.
Advance or Load. When sampled HIGH, the internal burst address counter will increment
in the order defined by the LBO input value. When LOW, a new address is loaded.
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a
WRITE operation. Is ignored when ADV/LD is HIGH.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
Burst order
Interleaved burst order (LBO = 1)
A1 A0
Starting address
First increment
Second increment
Third increment
0 0
0 1
1 0
1 1
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
00
Starting Address
First increment
Second increment
Third increment
Linear burst order (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
A1 A0
0 1
1 0
1 1
0 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
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v.1.3
Alliance Semiconductor
P. 5 of 19
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