EEWORLDEEWORLDEEWORLD

Part Number

Search

DFNA5001AT3

Description
RESISTOR, NETWORK, FILM, ISOLATED, 0.4 W, SURFACE MOUNT, 1616, SOIC, ROHS COMPLIANT
CategoryPassive components    The resistor   
File Size237KB,3 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance  
Download Datasheet Parametric View All

DFNA5001AT3 Overview

RESISTOR, NETWORK, FILM, ISOLATED, 0.4 W, SURFACE MOUNT, 1616, SOIC, ROHS COMPLIANT

DFNA5001AT3 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVishay
package instructionSMT, 1616
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresPRECISION
structureChip
Component power consumption0.1 W
The first element resistor5000 Ω
JESD-609 codee3
Installation featuresSURFACE MOUNT
Network TypeISOLATED
Number of components1
Number of functions4
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package height0.85 mm
Package length4 mm
Package shapeRECTANGULAR PACKAGE
Package formSMT
Package width4 mm
method of packingTR
Rated power dissipation(P)0.4 W
Rated temperature70 °C
resistance5000 Ω
Resistor typeARRAY/NETWORK RESISTOR
size code1616
surface mountYES
technologyTHIN FILM
Temperature Coefficient25 ppm/°C
Temperature coefficient tracking3 ppm/°C
Terminal surfaceMatte Tin (Sn)
Terminal shapeWRAPAROUND
Tolerance0.1%
Operating Voltage100 V
DFN
Vishay Thin Film
Dual Flat No Lead Molded
Precision Thin Film Resistor, Surface Mount Network
FEATURES
0.8 mm lead pitch
MSL level 1 per J-STD-020
Low profile 1 mm seated height
Small size 4 mm x 4 mm size 50 % board savings
over SOIC packages
Wide resistance range 100
Ω
to 100 kΩ available
Custom configurations available
Low TCR ± 25 ppm, TCR tracking to ± 3 ppm
Ratio tolerances to ± 0.025 %
Compliant to RoHS directive 2002/95/EC
The DFN series of precision surface mount resistor networks
feature isolated thin film precision resistors mounted in a
0.8 mm pitch 4 mm x 4 mm dual flat no lead package. The
networks feature 50 % savings in board space over
traditional SOIC packages. They are ideally suited for
applications of unity gain operational amplifiers that require
close TC tracking and tight ratio tolerances over
temperature. Custom configurations are available upon
request.
TYPICAL PERFORMANCE
ABSOLUTE
TCR
25
ABSOLUTE
TOL.
0.1
TRACKING
3
RATIO
0.05
SCHEMATIC
8
7
6
5
STANDARD RESISTANCE OFFERING
(R
1
=)
500
Ω
1 kΩ
2 kΩ
4.99 kΩ
5 kΩ
10 kΩ
20 kΩ
50 kΩ
100 kΩ
R
1
R
1
R
1
R
1
1
2
3
4
Note
• Consult factory for additional R values and schematics
STANDARD ELECTRICAL SPECIFICATIONS
TEST
Material
Pin/Lead Number
Resistance Range
TCR: Absolute
TCR: Tracking
Tolerance: Absolute
Tolerance: Ratio
Power Rating: Resistor
Power Rating: Package
Stability: Absolute
Stability: Ratio
Voltage Coefficient
Working Voltage
Operating Temperature Range
Storage Temperature Range
Noise
Thermal EMF
Shelf Life Stability: Absolute
Shelf Life Stability: Ratio
SPECIFICATIONS
Passivated nichrome
8
100
Ω
to 100 kΩ per resistor
± 25 ppm/°C
± 3 ppm/°C
± 0.05 % to ± 1.0 %
± 0.025 % to ± 0.5 %
100 mW
100 mW x number of resistors
ΔR
± 0.05 %
ΔR
± 0.015 %
< 0.1 ppm/V
100 V max. not to exceed
P
x
R
- 55 °C to + 125 °C
- 55 °C to + 150 °C
< - 30 dB
< 0.08 μV/°C
ΔR
± 0.01 %
ΔR
± 0.002 %
CONDITIONS
-
-
-
- 55 °C to + 125 °C
- 55 °C to + 125 °C
+ 25 °C
+ 25 °C
Maximum at + 70 °C
Maximum at + 70 °C
2000 h at + 70 °C
2000 h at + 70 °C
-
-
-
-
-
-
1 year at + 25 °C
1 year at + 25 °C
Document Number: 60109
Revision: 25-Jan-10
For technical questions, contact:
thinfilm@vishay.com
www.vishay.com
47
Modulesim - Altera simulation problem
The simulation settings and testbench writing are done according to the data , but there is no response when calling up modulessim-altera simulation. The lower left corner shows VSIM (paused), and the...
eeleader FPGA/CPLD
Problems encountered when debugging nandflash
This is the problem I encountered when debugging nandflash. The platform is: WinCE 5.0. The nandflash used is: K9F5608U0D. The board is mine, not Samsung. The controller is also different from Samsung...
joychow Embedded System
【BLE 5.3 wireless MCU CH582】9. Hardware SPI driver LCD
Series of articles: 【BLE 5.3 wireless MCU CH582】1. Getting to know the CH582 development board (unboxing) 【BLE 5.3 wireless MCU CH582】2. MounRiver IDE first experience 【BLE 5.3 wireless MCU CH582】3. N...
freeelectron Domestic Chip Exchange
PCB design flow chart: clear thinking is far more important than hard work
[size=4] Clear thinking is far more important than hard work! ! ! [/size] [size=4] I believe that many partners who have just come into contact with PCB do not have an accurate idea and plan in their ...
qwqwqw2088 PCB Design
Follow Guan Guan to visit the Shenzhen ELEXCON Electronics Exhibition: Round 2
I'm here again I'm here again~~Yesterday we shared the results of the first day of the exhibition. If you haven’t seen it yet, please go to the post on the right to check it outRound 1 Let’s take a lo...
okhxyyo Domestic Chip Exchange
How to prevent CE background page from being displayed after WinCE is started?
My application is set to start automatically after booting. How can I block the WINCE background interface displayed after booting and directly display the application interface?...
dww12304106 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1279  2219  973  1226  1724  26  45  20  25  35 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号