HYMD232M646DL8-J datasheet, PDF

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HYMD232M646DL8-J: Description200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP); Categorystorage storage; File Size248KB，23 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HYMD232M646DL8-J Overview

200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP)

HYMD232M646DL8-J Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	MODULE
package instruction	DIMM, DIMM200,24
Contacts	200
Reach Compliance Code	compli
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N200
memory density	2147483648 bi
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	200
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM200,24
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum slew rate	1.76 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	0.6 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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200pin Unbuffered DDR SDRAM SO-DIMMs based on 256Mb D ver. (TSOP)

This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR

SDRAMs in 400 mil TSOP II packages on a 200pin glass-epoxy substrate. This Hynix 256Mb D ver. based unbuffered

SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is

suitable for easy interchange and addition.

FEATURES

•

JEDEC Standard 200-pin small outline, dual in-line

memory module (SO-DIMM)

Two ranks 32M x 64 and One rank 32M x 64, 16M x

64 organization

2.6V

0.1V VDD and VDDQ Power supply for

DDR400, 2.5V

0.2V for DDR333 and below

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

133/166/200MHz

DLL aligns DQ and DQS transition with CK transition

Programmable CAS Latency: DDR266(2, 2.5 clock),

DDR333(2.5 clock), DDR400(3 clock)

•

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Edge-aligned DQS with data outs and Center-aligned

DQS with data inputs

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial Presence Detect (SPD) with EEPROM

Built with 256Mb DDR SDRAMs in 400 mil TSOP II

packages

Lead-free product listed for each configuration

(RoHS compliant)

ADDRESS TABLE

Organization

256MB

128MB

32M x 64

16M x 64

Ranks

SDRAMs

16Mb x 16

32Mb x 8

16Mb x 16

# of

DRAMs

# of row/bank/column Address

13(A0~A12)/2(BA0,BA1)/9(A0~A8)

13(A0~A12)/2(BA0,BA1)/10(A0~A9)

13(A0~A12)/2(BA0,BA1)/9(A0~A8)

Refresh

Method

8K / 64ms

PERFORMANCE RANGE

Part-Number Suffix

Speed Bin

CL - tRCD- tRP

CL=3

Max Clock

Frequency

CL=2.5

CL=2

-D43

DDR400B

3-3-3

200

166

133

-J

DDR333

2.5-3-3

166

133

-K

DDR266A

2-3-3

133

-H

DDR266B

2.5-3-3

133

Unit

MHz

Note:

1. 2.6V +/- 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V +/- 0.2V for DDR333 and below

Rev. 1.1 / May. 2005

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

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