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HYMD564M646BL6-D43

Description
200pin Unbuffered DDR SDRAM SO-DIMMs based on 512Mb B ver. (TSOP)
Categorystorage    storage   
File Size165KB,17 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HYMD564M646BL6-D43 Overview

200pin Unbuffered DDR SDRAM SO-DIMMs based on 512Mb B ver. (TSOP)

HYMD564M646BL6-D43 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSK Hynix
Parts packaging codeMODULE
package instructionDIMM, DIMM200,24
Contacts200
Reach Compliance Codecompli
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N200
memory density4294967296 bi
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals200
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX64
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM200,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.6 V
Certification statusNot Qualified
refresh cycle8192
self refreshYES
Maximum slew rate2.36 mA
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)2.6 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
200pin Unbuffered DDR SDRAM SO-DIMMs based on 512Mb B ver. (TSOP)
This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR
SDRAMs in 400mil TSOP II packages on a 200pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered
SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
JEDEC Standard 200-pin small outline, dual in-line
memory module (SO-DIMM)
Two ranks 64M x 64 organization
2.6V
±
0.1V VDD and VDDQ Power supply for
DDR400, 2.5V
±
0.2V for DDR333 and below
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
133/166/200MHz
DLL aligns DQ and DQS transition with CK transition
Programmable CAS Latency: DDR266(2, 2.5 clock),
DDR333(2.5 clock), DDR400(3 clock)
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial Presence Detect (SPD) with EEPROM
Built with 512Mb DDR SDRAMs in 400 mil TSOP II
packages
Lead-free product listed for each configuration
(RoHS compliant)
ADDRESS TABLE
Organization
512MB
64M x 64
Ranks
2
SDRAMs
32Mb x 16
# of
DRAMs
8
# of row/bank/column Address
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
Refresh
Method
8K / 64ms
PERFORMANCE
Part-Number Suffix
Speed Bin
CL - tRCD- tRP
CL=3
Max Clock
Frequency
CL=2.5
CL=2
-D43
1
DDR400B
3-3-3
200
166
133
-J
DDR333
2.5-3-3
-
166
133
-H
DDR266B
2.5-3-3
-
133
133
Unit
-
CK
MHz
MHz
MHz
Note:
1. 2.6V
±
0.1V VDD and VDDQ Power supply for DDR400 and 2.5V
±
0.2V for DDR333 and below
Rev. 1.1 / May. 2005
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
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