184pin Registered DDR SDRAM DIMMs based on 256Mb D ver. (TSOP)
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 400mil.
TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 256Mb D ver. based Registered DIMM series provide
a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange
and addition.
FEATURES
•
•
•
•
•
•
•
•
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
Two ranks 128M x 72, 64M x 72 and One rank 64M x
72, 32M x 72 organization
Error Check Correction (ECC) Capability
2.5V
±
0.2V VDD and VDDQ Power supply for
DDR333 and below
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100/133MHz
DLL aligns DQ and DQS transition with CK transition
Programmable CAS Latency : DDR200(2 clock),
DDR266(2, 2.5 clock)
•
•
•
•
•
•
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
Auto refresh and self refresh supported
8192refresh cycles / 64ms
Serial Presence Detect (SPD) with EEPROM
Built with 256Mb DDR SDRAMs in 400 mil TSOP II
packages
Lead-free product listed for each configuration
(RoHS compliant)
ADDRESS TABLE
Organization
256MB
512MB
512MB
1GB
32M x 72
64M x 72
64M x 72
128M x 72
Ranks
1
1
2
2
SDRAMs
32Mb x 8
64Mb x 4
32Mb x 8
128Mb x 4 (Stacked)
# of
DRAMs
9
18
18
36
# of row/bank/column Address
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
13(A0~A12)/2(BA0,BA1)/12(A0~A9,A11,A12)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
PERFORMANCE RANGE
Part-Number Suffix
Speed Bin
CL - tRCD- tRP
CL=3
Max Clock
Frequency
CL=2.5
CL=2
-K
DDR266A
2-3-3
-
133
133
-H
DDR266B
2.5-3-3
-
133
133
-L
DDR200
2-2-2
-
100
100
Unit
-
CK
MHz
MHz
MHz
Rev. 1.1 / May. 2005
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
184pin Registered DDR SDRAM DIMMs
ORDERING INFORMATION
Part Number
HYMD232G726D8-K/H
HYMD232G726DP8-K/H
HYMD232G726D8M-K/H
HYMD232G726DP8M-K/H
HYMD264G726D8-K/H
HYMD264G726DP8-K/H
HYMD264G726D8M-K/H
HYMD264G726DP8M-K/H
HYMD264G726D4-K/H
HYMD264G726DP4-K/H
HYMD264G726D4M-K/H
HYMD264G726DP4M-K/H
HYMD212G726DS4-K/H/L
HYMD212G726DSP4-K/H/L
HYMD212G726DS4M-K/H
HYMD212G726DSP4M-K/H
Density
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
Organization
32M x 8
32M x 8
32M x 8
32M x 8
64M x 8
64M x 8
64M x 8
64M x 8
64M x 4
64M x 4
64M x 4
64M x 4
128M x 4 (stacked)
128M x 4 (stacked)
128M x 4 (stacked)
128M x 4 (stacked)
# of DRAMs Material
9
9
9
9
18
18
18
18
18
18
18
18
36
36
36
36
Normal
Pb-free
1
Normal
Pb-free
1
Normal
Pb-free
1
Normal
Pb-free
1
Normal
Pb-free
1
Normal
Pb-free
1
Normal
Pb-free
1
Normal
Pb-free
1
DIMM Dimension
133.35 x 43.18 x 3.99 [mm
3
]
↑
133.35 x 30.48 x 3.99 [mm
3
]
↑
133.35 x 43.18 x 3.99 [mm
3
]
↑
133.35 x 30.48 x 3.99 [mm
3
]
↑
133.35 x 43.18 x 3.99 [mm
3
]
↑
133.35 x 30.48 x 3.99 [mm
3
]
↑
133.35 x 43.18 x 6.81 [mm
3
]
↑
133.35 x 30.48 x 6.81 [mm
3
]
↑
Note:
1. The “Pb-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability.
* These products are built with HY5DU564(8,16)22DT[P], the Hynix DDR SDRAM component.
Rev. 1.1 /May. 2005
2
184pin Registered DDR SDRAM DIMMs
PIN DESCRIPTION
Pin
CK0, /CK0
/CS0, /CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A13
A10/AP
BA0, BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0~8
Pin Description
Differential Clock Inputs
Chip Select Inputs
Clock Enable Inputs
Commend Sets Inputs
Address Inputs
Address Input/Autoprecharge
Bank Address
Data Inputs/Outputs
Data Check bits
Data Strobes
Data-in Masks
Pin
VDD
VDDQ
VSS
VREF
VDDSPD
VDDID
SA0~SA2
SCL
SDA
DU
NC
TEST
Pin Description
Power Supply for Core and I/O
Power Supply for DQs
Ground
Input/Output Reference
Power Supply for SPD
VDD, VDDQ Level Detection
SPD Address Inputs
SPD Clock Input
SPD Data Input/Output
Do not Use
No Connect
Reserved for test equipment use
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
NC,CK1
NC,/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Name
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC,/CS2
DQ48
DQ49
VSS
NC,/CK2
NC,CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Name
VSS
DQ4
DQ5
VDDQ
DM0,DQS9
DQ6
DQ7
VSS
NC
NC,TEST
NC,/FETEN
VDDQ
DQ12
DQ13
DM1,DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC,BA2
DQ20
NC,A12
VSS
DQ21
A11
DM2,DQS11
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3,DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8,DQS17
A10
CB6
VDDQ
CB7
Key
VSS
DQ36
DQ37
VDD
DM4,DQS13
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5,DQS14
VSS
DQ46
DQ47
NC,/CS3
VDDQ
DQ52
DQ53
NC,A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7,DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
note:
1. Pins 111, 158 are not used for single rank module.
2. Pin 167 is “NC” for 256MB, 512MB and 1GB or “A13” for 2GB module.
3. Pins 16, 17, 75, 71, 76, 102, 103, 113, 163 are not used on this module.
Rev. 1.1 /May. 2005
3
184pin Registered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB, 32Mb x 72 ECC Registered DIMM: HYMD232G726D[P]8[M]
/RS0
DQS0
DM0
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D0
D4
DQS1
DM1
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D1
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D2
D6
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D3
D7
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
/S0
BA0-BA1
A0-A13
/RAS
/CAS
CKE0
/WE
PCK
/PCK
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
SCL
VDDSPD
Serial PD
DO-D8
DO-D8
DO-D8
DO-D8
Strap:see Note 4
Serial PD
SDA
WP
A0
A1
A2
VDDQ
VDD
VREF
VSS
VDDID
D8
SA0 SA1 SA2
R
E
G
I
S
T
E
R
/RS0->/CS : SDRAMs D0-D8
RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D8
RA0-RA13-> : A0->A13 : SDRAMs D0-D8
/RRAS->/RAS : SDRAMs D0-D8
/RCAS->/CAS : SDRAMs D0-D8
RCKEO->CKE : SDRAMs D0-D8
/RWE->/WE : SDRAMs D0-D8
/RESET
CKO, /CKO------PLL*
* Wire per Clock Loading Table/Wiring Diagram
Note :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. V
DDID
strap connections (for memory device V
DD
, V
DDQ
) :
STRAP OUT (OPEN) : V
DD
= V
DDQ
STRAP IN (V
SS
) : V
DD
≠
V
DDQ
5. SDRAM placement alternates between the back and
front sides of the DIMM.
6. Address and control resistors should be 22 Ohms.
Rev. 1.1 /May. 2005
4
184pin Registered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]8[M]
/RS1
/RS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
/S0
/S1
BA0-BA1
A0-A13
/RAS
/CAS
CKE0
CKE1
/WE
PCK
/PCK
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VDDQ
DO-17
DO-D17
DO-D17
DO-D17
Strap:see Note 4
/CS
DQS
WP
A0
A1
A2
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQS
D0
D9
D4
D 1
D13
2
D1
D10
D5
D14
D2
D11
D6
D15
D3
D12
D7
D16
Serial PD
SCL
SDA
D8
D17
VDDSPD
SA0 SA1 SA2
Serial PD
R
E
G
I
S
T
E
R
/RCSO->/CSO : SDRAMs D0-D8
/RCS1->/CS1 : SDRAMs D9-D17
RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D17
RA0-RA13-> : A0->A13 : SDRAMs D0-D17
/RRAS->/RAS : SDRAMs D0-D17
/RCAS->/CAS : SDRAMs D0-D17
RCKEO->CKE : SDRAMs D0-D8
RCKE1->CKE : SDRAMs D9-D17
/RWE->WE : SDRAMs D0-D17
/RESET
VDD
VREF
VSS
VDDID
CKO, /CKO------PLL*
* Wire per Clock Loading Table/Wiring Diagram
Note :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. V
DDID
strap connections (for memory device V
DD
, V
DDQ
) :
STRAP OUT (OPEN) : V
DD
= V
DDQ
STRAP IN (V
SS
) : V
DD
≠
V
DDQ
5. RCS0 and RCS1 altermate between the back front sides of the DIMM.
6. Address and control resistors should be 22 Ohms.
Rev. 1.1 /May. 2005
5
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