HYMD512726BP8J-D43 datasheet, PDF

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HYMD512726BP8J-D43: Description1184pin Unbufferd DDR SDRAM DIMMs; Categorystorage storage; File Size367KB，30 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HYMD512726BP8J-D43 Overview

1184pin Unbufferd DDR SDRAM DIMMs

HYMD512726BP8J-D43 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
JESD-609 code	e6
memory density	9663676416 bi
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
power supply	2.6 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum slew rate	5.31 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	2.6 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Bismuth (Sn/Bi)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20

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184pin Unbuffered DDR SDRAM DIMMs based on 512Mb B ver.

This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil

TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered DIMM series provide

a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange

and addition.

FEATURES

•

JEDEC Standard 184-pin dual in-line memory module

(DIMM)

Two ranks 128M x 72, 128M x 64 and One rank 64M

x 72, 64M x 64, 32M x 64 organization

2.6V

0.1V VDD and VDDQ Power supply for

DDR400, 2.5V

0.2V for DDR333 and below

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

133/166/200MHz

DLL aligns DQ and DQS transition with CK transition

Programmable CAS Latency: DDR266(2, 2.5 clock),

DDR333(2.5 clock), DDR400(3 clock)

•

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Edge-aligned DQS with data outs and Center-aligned

DQS with data inputs

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial Presence Detect (SPD) with EEPROM

Built with 512Mb DDR SDRAMs in 400 mil TSOP II

packages

Lead-free product listed for each configuration

(RoHS compliant)

ADDRESS TABLE

Organization

256MB

512MB

1GB

32M x 64

64M x 64

64M x 72

128M x 64

128M x 72

Ranks

SDRAMs

32Mb x 16

64Mb x 8

128Mb x 8

# of

DRAMs

# of row/bank/column Address

13(A0~A12)/2(BA0,BA1)/10(A0~A9)

13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)

Refresh

Method

8K / 64ms

PERFORMANCE RANGE

Part-Number Suffix

Speed Bin

CL - tRCD- tRP

CL=3

Max Clock

Frequency

CL=2.5

CL=2

-D43

DDR400B

3-3-3

200

166

133

-J

DDR333

2.5-3-3

166

133

-H

DDR266B

2.5-3-3

133

Unit

MHz

Note:

1. 2.6V

0.1V VDD and VDDQ Power supply for DDR400 and 2.5V

0.2V for DDR333 and below

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.1 / May. 2005

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